Abstract: A SRAM including an array of memory cell lines and columns, each column being supplied between a high supply voltage and a low supply voltage, which includes at least one MOS transistor in series with each column, and circuitry for applying to the at least one MOS transistor a turn-off control signal to enter a stand-by mode, whereby the overall resistance of the column and of the at least one transistor increases in stand-by mode.

Abstract: A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.

Abstract: Presented is a method of enhancing the rate of removal of a photoresist layer from wafers of semiconductor material after the latter have gone through various process steps to define the patterns of integrated circuits. The method includes heating the wafer and treating it with low-pressure steam in a vacuum environment before starting to remove the photoresist by plasma or wet solutions. This pre-treatment of the photoresists allows the time for removing the photoresist to be reduced substantially and eliminates problems from residue.

Abstract: An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.

Abstract: A method for addressing redundant columns in a nonvolatile memory, which receives, at inputs, selection addresses and comprises a plurality of redundant columns, each including a respective bit line and a plurality of memory cells connected to the bit line. The addressing method comprises the steps of: detecting a transition in the selection addresses; starting charging of all the bit lines upon detection of the transition in the addresses; then detecting whether one of the redundant columns is addressed; should one of the redundant columns be found to be addressed, proceeding with charging of the bit line of the redundant column addressed and interrupting charging of the bit lines of the redundant columns not addressed; and should none of the redundant columns be found to be addressed, interrupting charging of all the bit lines.

Abstract: The definition of conversion of a digital value in a PWM signal using an N-bit up/down counter is improved by increasing the dimension of the input data to N+2 bits. This is done using the two Lsb's of the N+2 input data for selecting one among three intermediate levels between two consecutive values of an N-bit dynamic, according to a predefined table of combinations. The converter may still use an N-bit comparator. The system is particularly useful in driving a multi-phase brushless DC motor with each phase-winding singularly driven through a full-bridge output stage.

Abstract: During critical plasma etching steps, the wafer's surface is illuminated with electromagnetic radiation in the visible and/or in the UV spectrum having an energy and power density sufficient to increase the reverse current through protective junctions on the wafer. These protective junctions provide electrical discharge paths for electrical charges picked up by exposed conductive parts of the wafer. The induced voltages are limited to values compatible with preserving the integrity of functional dielectric layers coupled to the exposed conductive parts and to the semiconductor substrate or to another conductive part.

Abstract: Presented is a DC/DC converting circuit adapted to convert a DC input voltage to a DC output voltage. The converting circuit uses, as its synchronous rectifier member, a PMOS bipolar power transistor of the PMOS type, and allows it to be turned on by a control logic circuit capable of quickly sensing automatically the difference in electric potential between a conduction terminal and the body terminal of the transistor.

Abstract: The a timer circuit and oscillator are disclosed. The timer circuit is similar in functionality to a '555 timer circuit but uses few transistors. The timer circuit has two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter. The two differential pairs of transistors, three current mirrors, two selectable current sources, and one inverter are arranged to receive an IN+ voltage, an IN voltage, and a IN− voltage. From these inputs a Q and a Q(bar) output is generated. This timing circuit can be used to generate an oscillator by connecting a capacitor, a current source, and current drain to the IN voltage.

Abstract: The non volatile memory device integrates, in one and the same chip, the array of memory cells, a voltage regulator which supplies a regulated operating voltage to a selected word line, and a short circuit detecting circuit. The short circuit detecting circuit detects the output voltage of the voltage regulator, which is correlated to the current for biasing the cells of the word line selected. Once settled to the steady state condition, the output current assumes one first value in the absence of short circuits, and one second value in the presence of a short circuit between the word line selected and one or more adjacent word lines. The short circuit detecting circuit compares the output current of the voltage regulator with a reference value and generates at output a short circuit digital signal which indicates the presence or otherwise of a short circuit.

Abstract: A low frequency PWM output bridge amplifier having an input network configurable for standard PWM digital input signals, phase shift PWM digital input signals or analog input signals and for standard PWM output or phase shift PWM output is provided. The amplifier includes two identical amplifying modules. One for the amplifying channel relative to the direct or positive PWM output and the other for the amplifying channel relative to the inverted or negative PWM output. Each module includes a switching output operational amplifier, having a voltage mode noninverting input, a current mode inverting input and a loop filter implementing a single or multiple slope integrator outputting a signal of a substantially triangular waveform.

Abstract: A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

Abstract: The present invention relates to a method of manufacturing an avalanche diode of determined threshold in a substrate of a first conductivity type with a low doping level, including the steps of diffusing in the substrate at least one first region of the first conductivity type; diffusing in the substrate a second region of the second conductivity type protruding from the first region. The opening of a mask of definition of the first region has a lateral extent smaller than the diffusion depth of the first region in the substrate, this lateral extent being chosen all the smaller as the desired avalanche threshold is high.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: A structure for protection against electrostatic surges having two input terminals and two output terminals. The output terminals of the structure are connected to the inputs of a circuit to be protected. A first input terminal is connected to a first output terminal via an impedance. The second input terminal is connected to the second output terminal. The input terminals are interconnected by a first avalanche diode. The output terminals are interconnected by a second avalanche diode having the same biasing as the first avalanche diode.

Abstract: A device for synchronizing a reference event of an analog signal, which includes an analog-to-digital converter receiving an input signal, a register receiving the converter output, a phase-locked loop including an oscillator generating several phase-shifted clock signals of same period, a first clock signal clocking the register, a multiplexer receiving the other clock signals on respective inputs, the output of which clocks said converter, and an analysis circuit connected to control the multiplexer according to successive values of the register output.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called “smart power” type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: The drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures.

Abstract: The filter includes an arithmetical chain of parallel adders alternated with delay elements, and a memory constituted by lines of one-bit cells. Each line is addressable by a decoder controlled by a digital signal to be filtered; each line of memory contains side by side values which correspond to the partial products of successive impulse-response coefficients for a value equal to the line address. The memory additionally includes a number of read amplifiers. The number of read amplifiers is equal to the number of cells of one line in order to read the bits of the addressed. The outputs of the amplifiers are connected to respective parallel inputs of the adders of the arithmetical chain. Each memory line contains these values in two's-complement binary form in words which decrease in length by one bit for each increment of 2 in the characteristic of the coefficients, starting from the one of lowest characteristic.