Abstract: An electronic chip assembly having the following components: a substrate having electrical conductors therein; an electronic circuit chip affixed face down to the substrate so as to make electrical connection to the conductors; a male framing member, compliantly adhered to the substrate; a lid having a female channel, the channel having sidewalls, the channel being disposed on or within said lid for receiving said male framing member; and sealant material disposed within the channel between the sidewalls of said channel and the female lid sealing member.

Abstract: A book-like fixture and method for assembly of a plurality of multi-layered ceramic packages including a substrate and a cap. The fixture has a baseplate, a removable tray, an alignment plate for precisely aligning the caps with the substrates, a compression plate, and a plurality of compression devices designed to uniformly distribute compressive force on the plurality of packages. The fixture is preferably adapted for use of removable trays conforming to the Joint Electronics Design Engineering Council Tray Standard. The compression devices preferably have a spring, preferably a detachable leaf spring, and a compression plate placed over each cap. The structure of the fixture allows replacement of the springs and other modifications to allow assembly of multi-layered ceramic packages of differing dimensions. The structure of the fixture also allows stacking one on top of another.

Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.

Abstract: A gang punch tool assembly and method is provided for punching holes in a plurality of greensheets which are processed sequentially through the assembly. The punch mechanism is a gang punch cooperating with a corresponding die and the greensheet is automatically fed to the gang punch and die, the greensheet punched and then the punched greensheet removed from the punch area and another greensheet positioned for punching. Operation of the gang punch apparatus is efficient and effective and has a high greensheet throughput. A preferred gang punch uses a pressurizable air chamber for controlling punching of the greensheet without damage to the greensheets or gang punch mechanism.

Abstract: A metrology apparatus for determining bias and overlay errors in a substrate formed by a lithographic process includes an aperture between the objective lens and the image plane adapted to set the effective numerical aperture of the apparatus. The aperture is adjustable to vary the effective numerical aperture of the apparatus and the aperture may be non-circular, to individually vary the effective numerical aperture of the apparatus in horizontal and vertical directions. To determine bias and overlay error there is provided a target having an array of elements on the substrate, the array comprising a plurality of spaced, substantially parallel elements having a length and a width, the sum of the width of an element and the spacing of adjacent elements defining a pitch of the elements, edges of the elements being aligned along a line forming opposite array edges, the distance between array edges comprising the array width.

Abstract: A process of etching an oxide layer placed over a nitride layer of a substrate with high selectivity. The process comprises plasma etching the oxide layer of the substrate with a carbon and fluorine-containing gas and with a nitrogen-containing gas. A SixNy species is formed which is deposited on the nitride layer substantially in equilibrium with etching of the nitride layer.

Abstract: A process for forming multilevel metallization structures that improve semiconductor reliability. Multilevel metallization structures are formed through a two-step etch process which alleviates the problem of conductive etch residue forming between metal layers in multilevel structures. The resulting metallization structure has sidewall insulators on selected layers that prevent conductive etch residue from forming between the metal layers. The integration scheme of the present invention is especially applicable to metal-insulator-metal (MIM) capacitors.

Abstract: A method for obtaining equalization voltages that are a fraction of bit line high other than ½ in a DRAM semiconductor circuit, and an associated circuit, in arrangements that include a plurality of block cell arrays with a plurality of complementary pairs of bit lines connected to each block array with control lines to selectively activate a desired array block. Each block uses shared sense amplifiers connected to the pairs of bit lines and there is an equalization circuit connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit is also connected between each of the bit line pairs of each of the array blocks, between each of the array blocks and the shared sense amplifiers. A charge flow circuit control line is connected to the charge flow circuits for connecting the charge flow circuit to an electrical ground, thereby to act as a discharge circuit or to the bit line high voltage.

Abstract: A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Abstract: An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit.

Abstract: A process and apparatus for picking up and moving a microelectronic package during card assembly operations. A temporary lid having a top surface and a bottom surface attaches to at least one microchip on a substrate via a double-sided adhesive. The top surface of the lid provides a clean, smooth, flat surface to which a vacuum probe may be attached. After completion of the steps where vacuum probe movement is required, the lid and adhesive may be removed from the at least one microchip by pulling them both off together. No residue is left on the microchips.

Abstract: A copper-containing, wire-bonding pad structure for bonding to gold wires. The structure includes a nickel-containing film to improve metallurgical characteristics. The structure also has a laminated impurity film within the copper pad, which complexes with the nickel-containing pad to prevent a destructive interaction between nickel and copper at elevated temperatures, or during the lifetime of the device or the wirebond.

Abstract: A wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate and a process for manufacturing the same. The wire interconnect structure comprises an insulator layer disposed on an integrated circuit chip and an electrically conductive post extending through the insulator layer to the integrated circuit chip. The post has an elongated body, a bottom at one end of the body which is mechanically and electrically connected to the integrated circuit chip, and a top having a spherical shape at the opposite end of the body which extends outward from the insulator layer.

Abstract: A vertical channel field effect transistor and a process of manufacturing the same. The vertical channel field effect transistor is disposed on a surface of a substrate and comprises an epitaxial silicon stack having a bottom terminal comprising heavily doped silicon, a channel comprising lightly doped silicon of opposite doping type from the bottom terminal, and a top terminal comprising heavily doped silicon of the same doping type as the bottom terminal. The vertical channel field effect transistor also comprises a gate dielectric layer covering at least a portion of the bottom terminal, the channel, and the top terminal, and a gate in contact with the gate dielectric layer. The gate is positioned adjacent the channel and adjacent at least a portion of the bottom terminal and top terminal. The channel has a thickness between the bottom terminal and the top terminal from about 50 angstroms to about 800 angstroms.

Abstract: A process for estimating a critical dimension of a trench formed by etching a substrate. First, a regression model is constructed for estimating the critical dimension, in which principal component loadings and principal component scores are also calculated. Next, a substrate is etched and spectral data of the etching are collected. A new principal component score is then calculated using the spectral data and the principal component loadings. Finally, the critical dimension of the trench is estimated by applying the new principal component score to the regression model.

Abstract: A method of fabricating MOSFET devices in which the gate polysilicon is not consumed during damascene etch back, comprising: (a) forming a gate stack on a surface of a silicon-containing substrate, said gate stack having at least a pad oxide layer formed on said surface of said silicon-containing substrate and a nitride layer formed on said pad oxide layer; (b) forming a trough in said gate stack stopping on said pad oxide layer exposing a portion of said pad oxide layer, said trough having vertical sidewalls; (c) forming a conformal silicon layer on said gate stack and in said trough, including said vertical sidewalls and said exposed pad oxide layer; (d) removing the conformal silicon layer from said gate stack and said exposed pad oxide layer whereby silicon remains on the vertical sidewalls of said trough; (e) removing the exposed pad oxide from said trough exposing a portion of the silicon-containing substrate; (f) oxidizing the silicon on said vertical sidewalls of the trough and in said exposed silicon

Abstract: A structure and process for a triple damascene interconnection device. The device is formed within a terraced trench formed using damascene techniques within a single, relatively thick dielectric film. The interconnection device formed within the terraced structure includes a plurality of films and is a vertically coherent, redundant structure.

Abstract: A non-volatile random access memory (NVRAM) structure comprising an injector element in a single crystal silicon substrate; an insulator layer over the substrate; a silicon-on-insulator (SOI) layer over the insulator layer; and a sensing element in the SOI layer overlying the injector element. The NVRAM structure may further comprise a gate above the SOI layer, a floating gate in the insulator layer, or both.

Abstract: A device repair process that includes removing a passivation polyimide layer. The passivation polyimide layer is removed using a first-half ash followed by a second-half ash. The device is then cleaned using sodium hydroxide (NaOH) and a subsequent light ash step is implemented. After the passivation polyimide layer is removed, a seed layer is deposited on the device. A photoresist is formed on the seed layer and bond sites are formed in the photoresist. Repair metallurgy is plated through the bond sites. The bond sites are plated by coupling the device to a fixture and applying the current for plating to the fixture. The contact between the device and the fixture is made though bottom surface metallurgy. After plating, the residual seed layer is removed and a laser delete process is implemented to disconnect and isolate the nets of the device.

Abstract: A calibration wafer for precisely aligning a wafer-handling system that processes a plurality of product wafers. The calibration wafer has radial and thickness dimensions and tolerances equivalent to those of the product wafers and further comprises a first center marker adapted for alignment with a second center marker external to the calibration wafer. The calibration wafer may be a component of a wafer center alignment device for precisely aligning a wafer-handling system in a calibration location in relation to a wafer-processing tool, the device further comprising an alignment jig adapted to be repeatably mounted on the tool and on which the second center marker is located. The calibration wafer is adapted to be positioned so that the first center marker aligns with the second center marker.