Abstract: A structure for enhancing electromigration resistance within a copper film includes impurities laminated within the film and other additives incorporated in the film to form intermetallic compounds. Metal grain boundary growth and metal surface mobility is suppressed within the composite copper film. The present invention provides an alloy seed layer and laminated impurities and provides indium, tin, titanium, their compounds with oxygen, and their complexes with oxygen, carbon, and sulfur, incorporated into other films. Intermetallics are disposed at grain boundaries and reduce copper atom mobility. A further aspect of the present invention is a barrier layer formed by combining additives included in an alloy seed layer with materials otherwise unsuitable for barrier material functions.

Abstract: A semiconductor device or other suitable substrate and method with single or multi layers of buried micro pipes are disclosed. This is achieved by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer, and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes.

Abstract: A device and method for enabling the reworkability of an integrated circuit comprising a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.

Abstract: A gang-punch pin apparatus for punching selected hole patterns in thin sheet materials such as greensheets is provided. The gang-punch pin apparatus uses program plates in the punch apparatus which plates are positioned intermediate the non-punching end of the punch pins and a clearance plate wherein punch pins not used for punching a particular layer of the MLC are retracted into during punching. At the other punch pin locations, the punch pins, upon activation of the punch apparatus by compressing an expandable chamber, usually by application of a force on the punch apparatus, are extended through the lower portion of the punch apparatus to form vias in a greensheet. A die apparatus is also provided for use with the punch assembly to form the vias and to remove the punched material (slugs) from the die apparatus. The gang punch-pin may be shorter than conventional pins and be made at a low cost because of the thin sheet metal plates preferably used to make the component parts of the punch and die apparatus.

Abstract: The invention provides a stabilized integrated transimpedance amplifier comprising: an amplifier integrated on a substrate, coupling capacitors integrated into the amplifier substrate, the amplifier being adapted to have open loop amplification characteristics that compensate for changes in the capacitance of the capacitors with supply voltage of the amplifier.

Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

Abstract: A method of determining time-to-breakdown of a gate dielectric in an NFET or a PFET transistor. For an NFET transistor, the method includes providing an N+ injector ring in the p-substrate and forward biasing the N+ injector ring with respect to the p-substrate. A first positive reference voltage level is applied to the source and the drain regions. A second positive reference voltage level is applied to the gate dielectric. The first and second positive reference voltage levels are maintained on the transistor until breakdown of the gate dielectric occurs. Another embodiment of the method may be used in a PFET transistor.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A method determining the status of a feature (e.g., a semiconductor contact hole or trench) using a measurement imaging tool such as a scanning electron microscope (SEM). The method first assures that the waveform signal obtained from the SEM is reliable. A blanked beam signal, provided in saved images from the SEM, is the basis for a signal quality factor. This signal is provided in the waveform analyzed by the system. The method then analyzes all of the data between the edges of the feature and fits various functions to the data to determine which provides the best fit. Multiple linear regression and the r2 (quality of fit) factor, or some other type of correlation coefficient, are used to determine which function has the best fit. The feature is then characterized based on the particular function chosen and on the correlation factor obtained.

Abstract: A structure and process for a copper-containing, wire-bonding pad structure for bonding to gold wires. The structure includes a nickel-containing film to improve metal lurgical characteristics. The structure also has a laminated impurity film within the copper pad, which complexes with the nickel-containing pad to prevent a destructive interaction between nickel and copper at elevated temperatures, or during the lifetime of the device or the wirebond.

Abstract: A process for making metal lines in BEOL semiconductor devices. The process reduces metal voids in the metal lines. In one embodiment, metal lines, including a top barrier blanket are formed over an interlevel dielectric. An insulating layer having tensile stress is formed over the metal lines. A first compressive oxide layer is formed over the insulating layer, wherein the insulating layer provides a tensile stress on the metal lines and the compressive oxide layer provides a compressive stress on the metal lines resulting in reduction of metal voids. The compressive oxide layer is etched with a first type of gas until the insulating layer is reached. The insulating layer is etched with addition of gases to facilitate end-point detection. This second type of gas is monitored for an emission of species at an intensity level having a specific wavelength optical emission, and the etching is stopped when the intensity level is reached.

Abstract: A method for depositing materials on a surface, having the following steps: a) obtaining a surface having at least feature thereon, the surface and the feature having a layer of first material deposited thereon, the first material not filling substantially all of the feature; b) depositing a layer of a second material on the first material, wherein the melting point of the second material is less than that of the first material, and wherein the first material is soluble in the second material at a temperature less than the melting point of the first material; and c) heating the surface to a first temperature of at least equal to the melting point of the second material and at most equal to the melting point of the first material, wherein substantially all of the via is filled with the first material.

Abstract: An electrical connector or interposer for making connection in a high density device electronic environment. The connector is made of a high density array of nickel columns held in a layer of polyimide with each column extending beyond the opposing surfaces of said layer of polyimide. The connector may be used to make temporary or permanent connection to electrical contacts without alignment. Connection may be accomplished by loading forces sufficient to form either an indentation or a penetration of solder ball contacts. Contact to a single chip or a full wafer of chips is facilitated for testing.

Abstract: The present invention discloses a high speed programmable electronic current driver circuit for supplying a controlled modulated current to an LED comprising: a current driver operable over a selectable range of current levels for connection to an LED for supplying operating current to an LED; control means connected to the current driver to select the current level for operation of the current driver; transmission gating means connected to the current driver to gate high speed data signal pulses to the current driver to modulate the current of the current driver by the data signal pulses by gating the current of the current driver with the data signal pulses; whereby light output by the LED will be modulated by the data signal pulses at selectable current levels.

Abstract: A method of making at least one feature on an object having an upper surface, comprising the steps of:1. applying a layer of a photoresist having an initial thickness to the upper surface;2. exposing the layer of photoresist to a first dosage of light having a first intensity for a first predetermined period of time, such that at least a portion of the upper surface has a thickness that is at most equal to the initial thickness; and3. exposing the layer of photoresist to a second dosage of light having a second intensity for a second predetermined period of time, such that at least a subset of the portion of the upper surface exposed by the first dosage of light is exposed by the second dosage of light.

Abstract: A brazing method for the direct bonding of a metallic item to a refractory metal without the need for an adhesion layer. The direct brazing process uses a Cu--Ag--Ni alloy which eliminates the need for the steps of plating a refractory metal to be bonded to a metallic material with a nickel layer (or other nickel-containing adhesion layer) and diffusion annealing the plated refractory metal prior to brazing. The brazed joint produced by the direct brazing method between a refractory metal and a metallic item has a substantially reduced layer of nickel in the as-brazed joint which improves the mechanical properties of the joint.

Abstract: The disclosed invention provides for a method of manufacturing solder columns for particular use in attaching substrates to a printed circuit board. The method results in columns of homogeneous composition and thus overcomes problems associated with the phenomena of segregation. The method includes the steps of forming particles of the metal composition to be used for the columns from a molten source of the composition. The solid particles are then formed into segments of homogeneous composition by drawing ingots of the composition into wire and severing the wire into segments.

Abstract: A method for establishing electrical communication between a first and second object, comprising the steps of 1) obtaining a first object in electrical communication with at least one BLM, each at least one BLM in contact with a high melting point solder ball coated with a low melting point solder, the low melting point solder contacting each solder ball over at least the portion of the solder ball not in contact with the BLM; 2) interacting a second object having at least one attachment point, each at least one attachment point corresponding to at least one solder ball on the first object where electrical communication is desirable, each solder ball and corresponding attachment point are proximally situated such that each solder ball is capable of forming an electrical communication with the corresponding attachment point; and 3) reflowing the first object and the second object while the first object and the second object are interacted, such that the first object and the second object are in electrical comm

Abstract: This invention relates to a method for improving the chemical and electrical performance characteristics of a high dielectric constant material. The method comprises the steps of first obtaining a barium containing high dielectric constant material, the material having an upper surface and then modifying the surface chemistry of said upper surface by interacting said upper surface with a gas reactant in a closed environment. In a variant of the method, the gas reactant preferentially reacting with upper surface as compared to the bulk.

Abstract: A method of forming a solder ball structure comprising the steps of 1) obtaining a first object having at least one high melting point solder ball, each solder ball having a corresponding BLM containing a low melting point solder, each solder ball having an outer surface, top and bottom, each BLM having a top and bottom, the bottom of each solder ball in contact with the top of the corresponding BLM over a portion of the outer surface, the bottom of each BLM in electrical communication with the first object; 2) obtaining a template having a first surface; 3) applying a disjoint area of low melting point solder paste to the first surface of the template; 4) interacting the top of each solder ball and the solder paste; and 5) reflowing each solder ball and disjoint area of solder paste while each solder ball and disjoint area of solder paste are interacted.