Abstract: Various methods of fabricating a tungsten conductor structure are provided. In one aspect, a method of fabricating a tungsten conductor structure in an opening in an insulating film is provided that includes forming a titanium nitride film in the opening and heating the a titanium nitride film. The titanium nitride film is exposed to a flow of hydrogen gas and a flow of an inert carrier gas. The titanium nitride film is exposed to a flow of silane at a first flow rate for a first time interval and to a flow of tungsten hexafluoride for a second time interval that begins after the beginning but prior to the end of the first time interval. The flow of silane is reduced at the end of the first time interval to a second flow rate and maintained at the second flow rate for a third time interval. Fluorine diffusion into the titanium nitride film and the potential for void formation due to non-conformal tungsten deposition are reduced.

Abstract: A tungsten gate electrode and method of fabricating the same are provided. In one aspect, a method of fabricating a circuit device in an opening in an insulating film on a substrate is provided. The method includes depositing a film of amorphous silicon and amorphous tungsten in the opening, and thereafter depositing a film of polycrystalline tungsten on the film and annealing the substrate to react the amorphous silicon with the amorphous tungsten to form tungsten silicide on the insulating film and to increase the grain structure of the polycrystalline tungsten film. The tungsten silicide film and the polycrystalline tungsten film may be planarized to the insulating film. The method enables the seamless fabrication of an adhesion layer and a tungsten conductor structure in a single chamber and without resort to titanium.

Abstract: Integrated circuits with transistors exhibiting improved junction capacitances and various methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a doped region in an active area of a substrate wherein the doped region has a first conductivity type and a first horizontal junction. A first source/drain region of the first conductivity type is formed in the active area with a second horizontal junction. A second source/drain region of the first conductivity type is formed in the active area with a third horizontal junction and a lateral separation from the first source/drain region that defines a channel region. The second and third horizontal junctions are positioned substantially at the first horizontal junction. The portion of the doped region positioned in the channel region is doped with an impurity of a second conductivity type that is opposite to the first conductivity type.

Abstract: Methods of optimizing a preheat recipe for rapid thermal processing workpieces are provided. In one aspect, a method of manufacturing is provided that includes preheating a rapid thermal processing chamber according to a preheating recipe and processing a first plurality of workpieces in the rapid thermal processing chamber. Parameter measurements are performed on a first workpiece and a second workpiece of the first plurality of workpieces. The parameter measurements are indicative of processing differences between the first and second workpieces. An output signal is formed corresponding to the parameter measurements and a control signal based on the output signal is used to adjust the preheating recipe for preheating the rapid thermal processing chamber for processing a second plurality of workpieces in the rapid thermal processing chamber to reduce processing differences between first and second workpieces of the second plurality of workpieces.

Abstract: An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in a substrate and forming a first insulating sidewall in the trench and a second insulating in the trench in spaced-apart relation to the first insulating sidewall. A bridge layer is formed between the first and the second sidewalls. The bridge layer, the first and second sidewalls, and the substrate define an air gap in the trench. The isolation structure exhibits a low capacitance in a narrow structure. Scaling is enhanced and the potential for parasitic leakage current due to non-planarity is reduced.

Abstract: Methods of fabricating an isolation structure on a substrate are provided. In one aspect, a method of fabricating an isolation structure on a substrate is provided that includes forming a first insulating layer on the substrate wherein the first insulating layer has a first sidewall. A trench is formed in the substrate that has a second sidewall. A second insulating layer is formed in the trench. The second insulating layer displaces the second sidewall laterally. The first insulating layer is densified by heating to liberate gas therefrom and thereby move the first sidewall into substantial vertical alignment with the second sidewall. The risk of substrate attack due to trench isolation structure pullback is reduced. Trench edges are covered by thick isolation material.

Abstract: Various methods of fabricating gate structures, such as gates and gate stacks are provided. In one aspect, a method of fabricating a gate electrode on a substrate is provided that includes depositing a polycrystalline silicon film on the substrate and etching the polycrystalline film into a desired shape with a first sidewall and a second and opposite sidewall. A passivating oxide film is formed with a preselected thickness on the first and second sidewalls by oxidizing the silicon structure with a heated aqueous solution of ammonium hydroxide and hydrogen peroxide. Gate electrode formation with an oxide coating film of known thickness is provided. Linewidth metrology accuracy may be improved.

Abstract: A method of fabricating a buried local interconnect in a substrate and an integrated circuit incorporating the same are provided. The method includes the steps forming a trench in the substrate and forming a first insulating layer in the trench. A conductor layer is formed on the first insulating layer. A portion of the conductor layer is removed to define a local interconnect layer and a second insulating layer is formed in the trench covering the local interconnect layer. The method provides for a local interconnect layer buried beneath a dielectric layer of an integrated circuit, such as a shallow trench isolation layer. Areas of a substrate above the silicon-silicon dioxide interface formerly reserved for local interconnect layers in conventional processing may now be used for additional conductor lines.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate dielectric layer on the substrate and forming a gate electrode on the gate dielectric layer with a lower surface, a midpoint, and a quantity of p-type impurity. A quantity of nitrogen is introduced into the gate electrode whereby the quantity nitrogen has a peak concentration proximate the lower surface. A quantity of germanium is introduced into the gate electrode and first and second source/drain regions are formed in the substrate. The method enables simultaneous formation of n-channel and p-channel gate electrodes with work functions tailored for both types of devices.

Abstract: Methods of fabricating interconnects of aluminum and aluminum alloys are provided. In one aspect, a method is provided for fabricating an interconnect of aluminum-containing material on a surface. A layer of aluminum-containing material is deposited on the surface. The layer of aluminum-containing material is masked with selected portions thereof left exposed. A first etch of the exposed portions is performed in a plasma ambient containing BCl3, Cl2, N2 and CF4 to establish a plurality of trenches having inwardly sloping sidewalls. An overetch of the exposed portions is performed to the surface in a plasma ambient. High aspect ratio lines may be formed with sloped sidewalls that facilitate subsequent interlevel dielectric formation.

Abstract: A variable buoyancy cable is provided. In one aspect, the variable buoyancy cable includes a flexible sleeve that has an inner wall and an outer wall. A core is positioned in the sleeve and has a longitudinally disposed external channel with opposing first and second sidewalls. The channel and the inner wall of the flexible sleeve define a fluid passage for receiving a fluid to affect the buoyancy of the variable buoyancy cable. A slackened utility line is positioned in the channel and a fluid supply is coupled to the flexible sleeve and is operable to move fluid into and out of the fluid passage to selectively affect the buoyancy of the variable buoyancy cable. The core protects utility lines in the cable from damage due to ambient pressure and/or bending during deployment and retrieval. The buoyancy may be varied to suit various water conditions and mission requirements.

Abstract: Methods and apparatus for chemical mechanical polishing of substrates, such as semiconductor wafers, which employ retaining rings to hold a substrate in place during the polishing process. The retaining rings have surface characteristics that may be used to improve polishing uniformity, especially at a wafer periphery, and/or to improve removal rate of a chemical mechanical polishing (“CMP”) system. The surface characteristics may be recesses and/or protrusions on the pad-facing surface of a CMP retaining ring, which during polishing contact and act to flatten a CMP polishing pad beneath the substrate. Near the edge the surface characteristics may also condition the surface of a polishing pad during polishing and may be further configured to improve slurry transport.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas of the substrate. Each of the transistors has a doped region positioned in the substrate, an insulating layer positioned in a tapered trench in the substrate that extends through and sub-divides the doped region into a first source/drain region and a second source/drain region. The insulating layer is channel-shaped with a base, a first upwardly sloping sidewall and a second upwardly sloping sidewall. A gate electrode is positioned on the insulating layer. The channel-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate. The sloped sidewalls double as spacers, enabling process simplification.

Abstract: A transistor and a method of making the same are provided. The transistor includes a substrate and a gate dielectric layer positioned on the substrate that has first and second sidewall spacers. A gate electrode is positioned on the gate dielectric layer between the first and second sidewall spacers. A semiconductor layer is positioned on the substrate and adjacent the gate dielectric layer. First and second source/drain regions are provided wherein each of the first and second source/drain regions has a first portion positioned in the semiconductor layer and a second portion positioned in the substrate. Processing of the gate dielectric layer and the sidewall spacers is integrated.

Abstract: Methods of fabricating ohmic contacts and adhesion layers therefore are provided. In one aspect, a method of fabricating an ohmic contact in an opening of an insulating layer is provided. Tetra-dimethyl-amino-titanium vapor is decomposed in the presence of the opening to deposit TiCN in the opening at a rate of about 9.4 to 10.6 Å/second and a thickness of less than about 105 Å. The deposited TiCN is exposed to a plasma ambient containing nitrogen and hydrogen to remove carbon and oxygen from the deposited TiCN. A conducting material is deposited on the TiCN. Controlled TiCN thickness, and subsequent plasma treatment dissociate most of the carbon and oxygen incorporated into the TiCN layer during deposition. The potential for undesirably high contact resistance due to oxygen and carbon-based insulating structures within the adhesion layer is reduced.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. In one aspect, the method includes the steps of forming a gate insulating layer on the substrate with a first outwardly tapered sidewall and a second outwardly tapered sidewall. A gate electrode is formed on the gate insulating layer. A first source/drain region and a second source/drain region are formed in the substrate by implanting ions into the substrate, wherein a first portion of the ions passes through the first sidewall and a second portion of the ions passes through the second sidewall. The method provides for incorporation of spacer-like structure into a gate dielectric layer. Conventional spacer fabrication may be eliminated and graded source/drain regions established with a single implant.

Abstract: Methods of fabricating a silicide layer on a substrate or transistor structures thereon are provided. An exemplary method includes the steps of depositing a layer of metal on a substrate that has a pn junction. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer. Any unreacted metal is removed. The substrate and the silicide layer are heated above the agglomeration threshold temperature of any filaments of the silicide layer penetrating the pn junction but below the agglomeration threshold temperature of the silicide layer. The method eliminates silicide filaments, particularly in cobalt silicide processing, that can otherwise penetrate the pn junction of a transistor source/drain region a lead to reverse-bias diode-leakage currents.

Abstract: Various vascular filters are provided. In one aspect, a vascular filter is provided that includes a tubular sleeve and a core positioned in the sleeve that is axially deployable therefrom. A shape-memory wire is spiraled around the core and has a first portion unfurled from the core to define a hoop. The hoop is expandable from a retracted shape to a expanded shape when the core is deployed from the sleeve. A filter is provided that has a first end coupled to the core and a rim coupled to the hoop. The integration of the hoop with the shape-memory wire provides for excellent tip flexibility with enhanced resistance to structural failure.

Abstract: Various apparatus for CMP processing of workpieces are provided. In one aspect, a CMP tool is provided that includes a polish pad for polishing a workpiece and a head assembly for holding the workpiece during polishing. A fluid dispenser is also provided for dispensing a fluid to process the workpiece. The fluid dispenser has a housing and a tube coupled to the housing for dispensing a semiconductor processing fluid. The tube has a first end that is operable to move from a first elevation to a second elevation. A first shape memory member is provided that has a first end coupled to the housing and a second end coupled to the tube. The shape memory member is operable to deform in response to a thermal stimulation to selectively move the tube from the first elevation to the second elevation. The tool provides selective dispersal of processing fluids on a CMP polish pad or other processing surface is before, during and after CMP or other processes.

Abstract: An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.