Abstract: A transistor and a method of making the same are provided. The method includes the steps of forming a gate dielectric stack on the substrate that has a gate dielectric layer and forming first and second sidewall spacers adjacent the gate dielectric stack. A first portion of the gate dielectric stack is removed while a second portion thereof is left in place. First and second source/drain regions are formed in the substrate, and a conductor layer is formed over the first and second source/drain regions and on the second portion of the gate dielectric stack. The gate dielectric may be composed of a high dielectric constant material with a thin equivalent thickness of oxide. The method enables integrated processing of the gate electrode and source/drain metallization.

Abstract: An integrated circuit employing both sides of a base substrate or wafer and a method of making the same are provided. In one aspect, the integrated circuit includes a base substrate that has a first side and a second side opposite the first side. The first side has a first semiconductor layer and a first isolation structure positioned thereon wherein the first side surrounds the first semiconductor layer. The second side has a second semiconductor layer and a second isolation structure positioned thereon wherein the second isolation structure surrounds the second semiconductor layer. A first circuit device is positioned on the first semiconductor layer. A second circuit device is positioned on the second semiconductor layer. The method enables simultaneous processing of both sides of a given wafer. Fabrication efficiency is increased through higher throughput and much higher yields per wafer.

Abstract: Various methods of fabricating a circuit structure utilizing silicon nitride are provided. In one aspect, a method of fabricating a circuit structure is provided that includes forming a silicon nitride film on a silicon surface, annealing the silicon nitride film in an ammonia ambient and annealing the silicon nitride film in a nitrous oxide ambient to form a thin oxide layer at an interface between the silicon nitride film and the silicon surface. The process of the present invention enables the manufacture of thin silicon nitride films with highly uniform morphology for use as gate dielectrics or other purposes. The thin oxide film is self-limiting in thickness and improves differential mechanical stresses.

Abstract: An integrated circuit and a method of making the same are provided. The circuit includes a substrate that has a trench formed therein defining and isolating first and second active area and an upper surface. The circuit includes a capacitor that has a first insulating layer formed in the trench, a conductor layer formed on the first insulating layer, and a second insulating layer formed on the first insulating layer that fills the trench. The conductor layer is positioned substantially at or below the upper surface. The circuit integrates trench isolation structure with a capacitor that may be used as a filter between power and ground. The method integrates capacitor formation with trench isolation formation.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first layer and the second stack has a second layer and third and fourth spacers adjacent to the second layer. A gate dielectric layer is formed on the substrate between the first and second stacks and a first conductor layer is formed on the gate dielectric layer. A first source/drain region is formed beneath the first conductor layer and a second source/drain region is formed beneath the second conductor layer. The first and second layers are removed and a first contact is formed on the first source/drain region and a second contact is formed on the second source/drain region.

Abstract: Various methods of fabricating a silicide layer, and devices incorporating the same are provided. In one aspect, a method of fabricating a silicide layer on a substrate is provided. The method includes the steps of damaging the crystal structure of a portion of the substrate positioned beneath the spacer and depositing a layer of metal on the substrate. The metal layer and the substrate are heated to react the metal with the substrate and form the silicide layer, whereby a portion of the silicide layer extends laterally beneath the spacer. Any unreacted metal is removed. The method enables fabrication of silicide layers with substantial lateral encroachment into LDD structures, resulting in lower possible source-to-drain resistance and enhanced performance for transistors.

Abstract: Various methods of fabricating a reticle are provided. In one aspect, a pattern of opaque structures is formed on a plate capable of transmitting electromagnetic radiation. Adjacently positioned angled surfaces of the opaque structures are identified. Preselected portions of the opaque structures that encompass the adjacently positioned angled surfaces are then removed by ion-beam milling or other methods. Reticle patterns may be customized by modifying the structures of adjacent polygon structures that could otherwise give rise to diffraction-induced patterning errors on resist layers.

Abstract: An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.

Abstract: An isolation structure and a method of making the same are provided. In one aspect, the method includes the steps of forming a trench in the substrate and a first insulating layer in the trench that has a bottom, a first sidewall and a second sidewall. Silicon nitride is deposited in the trench. Silicon nitride is removed from the bottom of the first insulating layer to establish a layer of silicon nitride on the first and second sidewalls by performing a first plasma etch of the deposited silicon nitride with an ambient containing He, SF.sub.6, and HBr, and a second plasma etch with an ambient containing He, SF.sub.6, and HBr. An insulating material is deposited in the trench. The method provides for reliable manufacture of nitride liners for trench isolation structures. Scaling is enhanced and the potential for parasitic leakage current due to liner oxide fracture or irregularity is reduced.

Abstract: A transistor and a method of making the same are provided. The transistor includes a substrate that has an upper surface and a gate dielectric layer positioned on the substrate that has a first quantity of nitrogen therein. A gate electrode is positioned on the gate dielectric layer. First and second source/drain regions are positioned in the substrate and laterally separated to define a channel region beneath the gate dielectric layer. The gate dielectric layer may be composed of a high K material with a thin equivalent thickness of oxide, such as TiO.sub.2, Ta.sub.2 O.sub.5, CrO.sub.2 or SrO.sub.2. The nitrogen suppresses later oxide formation which may otherwise increase the equivalent thickness of oxide of the gate dielectric layer. Nitrogen may also be incorporated into the substrate and the gate electrode.

Abstract: Apparatus and method for depositing fluids on both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel and that is operable to rotate the mandrel. The apparatus also includes means for dispensing a first volume of fluid on the semiconductor wafer and a second volume of fluid on the semiconductor wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel. The mandrel is rotated to spin the semiconductor wafer and a semiconductor processing fluid is sprayed on the first and second sides of the semiconductor wafer.

Abstract: Apparatus and method for polishing one or both sides of a semiconductor wafer that has a central opening are provided. In one aspect, the apparatus includes a mandrel for holding the wafer and a motor coupled to the mandrel that is operable to rotate the mandrel. A first polisher assembly is provide that has a first polish pad for polishing the first side of the wafer and a second polish pad for polishing the second side of the wafer, and first means for moving the first and second polish pads into and out of engagement with the first and second sides of the wafer. According to the method, a semiconductor wafer is coupled to a rotatable mandrel and a polishing mixture is dispensed on one or both of the sides of the semiconductor wafer. A first polish pad is brought into contact with the first side of the semiconductor wafer and a second polish pad is brought into contact with the second side of the semiconductor wafer such that the first and second polish pads are positioned in opposition.

Abstract: A transistor and a method of making the same are provided. The method includes the step of forming a gate dielectric layer on the substrate where the gate dielectric layer is composed of an aluminum oxide containing material. A gate electrode is formed on the gate dielectric layer and first and second source/drain regions are formed in the substrate laterally separated to define a channel region beneath the gate electrode. The aluminum oxide containing material may be, for example, Al.sub.2 O.sub.3. Aluminum oxide provides for a gate dielectric with a thin equivalent thickness of oxide in a potentially single crystal form.

Abstract: An integrated circuit and a method of fabricating the same in a substrate are provided. A trench is formed in the substrate. The trench has a sidewall. A first insulating layer is formed on the sidewall. A gate electrode is formed on the first insulating layer. A first source/drain region is formed in the substrate and a second source/drain region is formed in the substrate. A first portion of the first source/drain region and a second portion of the second source/drain region are vertically spaced apart to define a channel region in the substrate. The process enables channel lengths to be set independent of the maximum resolution of the photolithographic system used to pattern the wafer. Very short channel lengths may be implemented.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The integrated circuit includes a substrate and a plurality of transistors positioned on a plurality of active areas. Each of the transistors has a gate dielectric layer with a V-shaped cross-section positioned on one of the plurality of active areas, a gate electrode positioned on the gate dielectric layer, a first source/drain region positioned in the substrate, and a second source/drain region positioned in the substrate in spaced-apart relation to the first source/drain region to define a channel region beneath the gate dielectric layer. The V-shaped gate dielectric layer requires less horizontal substrate area, enabling higher packing density for a given substrate.

Abstract: A integrated circuit transistor that has a high nitrogen concentration in the channel region and a method of making same are provided. A sacrificial oxide layer integrated with a nitrogen bearing species is grown on the substrate. A portion of the nitrogen bearing species diffuses into the substrate to form a nitrogen doped region. Nitrogen is implanted through the first oxide layer to increase the peak concentration of nitrogen in the nitrogen doped region. The sacrificial oxide layer is removed and a very thin gate oxide layer is formed. A gate, a source, and a drain are formed. The result is an integrated circuit transistor with a very thin gate oxide layer and a high peak concentration of nitrogen substantially at the Si--SiO.sub.2 interface.

Abstract: A seismic sensor pod is provided for coupling to a seismic cable and establishing a substantially water tight connection between the seismic cable and a seismic sensor. The pod includes a housing for holding the seismic sensor. The forward section of the housing includes a substantially sealed chamber. One or more conductors from the seismic cable are cut and the cut ends are projected into the chamber. Electrical connection between the cut ends of the conductors and the seismic sensor is established by a connector member. The pod provides a water resistant pathway between the conductors of the seismic cable and the seismic sensor, and a streamlined housing to hold the seismic sensor.

Abstract: An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

Abstract: An integrated circuit transistor and method of making the same are provided. The transistor includes a substrate, first and second source/drain regions, and a gate electrode stack coupled to the substrate. The gate electrode stack is fabricated by forming a first insulating layer on the substrate, forming a first conductor layer on the first insulating layer, and forming a metal layer on the first conductor layer. A second insulating layer, such as an interlevel dielectric layer, is coupled to the substrate adjacent to the gate electrode stack. Sidewall spacers and LDD processing may be incorporated. The transistor and method integrate metal and polysilicon into a self-aligned gate electrode stack.

Abstract: A semiconductor wafer incorporating process control monitors and a method of incorporating the same are provided. In one aspect, the semiconductor wafer has a plurality of fields formed in a pattern thereon that is subdivided into n zones and has a center point. The semiconductor wafer is provided with a plurality of integrated circuits each of which is positioned in one of the plurality of fields. The semiconductor wafer also includes a plurality of diagnostic integrated circuits dispersed in a pattern.