Patents Represented by Attorney, Agent or Law Firm Trask, Britt & Rossa
  • Patent number: 6125947
    Abstract: Rotary drag bits with enhanced formation cuttings removal achieved by apportioning drilling fluid flow in relationship to cuttings volume generated by various groups of cutters on the bit, each cutter group being located on a different blade of the bit. The flow apportionment may be effected by selective placement of nozzles on the bit face, employing different sized nozzles, by varying the orientation of similarly-sized nozzles, or by a combination of approaches. In addition, the transverse cross-sectional areas of the junk slots associated with each of the various blades are sized in similar proportion to the formation cuttings volume removed by each of the cutter groups. Finally, cuttings volumes from each blade of a particular type or category, such as primary, secondary, tertiary, are substantially mutually balanced with the volumes of the other blades of the same type or category.
    Type: Grant
    Filed: September 19, 1997
    Date of Patent: October 3, 2000
    Assignee: Baker Hughes Incorporated
    Inventors: William R. Trujillo, Craig H. Cooley
  • Patent number: 6127096
    Abstract: A semiconductor wafer having a first layer and overlying insulating layer receives a photoresist layer. A first photoresist area is exposed to light having a first dosage, while a second, adjacent photoresist area is concurrently exposed to light having a second dosage. The first area and second area then are concurrently developed to partially expose the photoresist layer. The partial exposure removes photoresist within the first area to one depth and within the second area to a second depth. The second depth differs from the first depth. In one embodiment, the second depth extends through the photoresist down to the insulating layer. After subsequently performing a contact and/or trench etch through the exposed insulating layer and removing excess photoresist above the insulating layer, conductive material is deposited in the contact/trench opening and over the insulating layer. The result is an upper conductive layer coupled to the first layer via a contact or other conductive connection.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: October 3, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Nanseng Jeng, Christophe Pierrat
  • Patent number: 6126062
    Abstract: A leadframe clamping apparatus includes a resilient polymeric membrane which permits self-leveling compensation of a variably movable clamp insert for variations in leadframe thickness. The clamp insert is formed of a polymer such as polyimide to provide further compensation for leadframe variations.
    Type: Grant
    Filed: April 2, 1998
    Date of Patent: October 3, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Sven Evers, Craig T. Clyne
  • Patent number: 6128518
    Abstract: The hematocrit of blood (i.e., the percentage of whole blood volume occupied by red blood cells) perfusing a finger is determined by stimulating the finger with two current frequencies, one relatively high (e.g., 10 MHZ) and the other relatively low (e.g., 100 KHz). Voltages induced in the finger in response to the two current frequencies are then captured and separated into baseline and pulsatile components. The hematocrit is determined as a function of the ratio of the high frequency pulsatile component to the low frequency pulsatile component, multiplied by the ratio of the square of the low frequency baseline component to the square of the high frequency baseline component. The signal-to-noise ratio of the captured voltages can be enhanced by the application of external pressure to the finger, such as by applying a pressure cuff to the finger.
    Type: Grant
    Filed: July 23, 1998
    Date of Patent: October 3, 2000
    Assignee: Microcor, Inc.
    Inventors: Robert Gail Billings, Justin S. Clark, Ke-shieng Yang, Jon Neese, Allan L. Kaminsky
  • Patent number: 6124665
    Abstract: A method of fabricating row lines over a field emission array. The method employs only two mask steps to define row lines and pixel openings through selected regions of each of the row lines. In accordance with the method of the resent invention, a layer of conductive material is disposed over a substantially planarized surface of a grid of semiconductive material. A layer of passivation material is then disposed over the layer of conductive material. In one embodiment of the method, a first mask may be employed to remove passivation material and conductive material from between adjacent rows of pixels and from substantially above each of the pixels of the field emission array. A second mask is employed to remove semiconductive material from between the adjacent rows of pixels. In another embodiment of the method, a first mask is employed to facilitate removal of passivation material, conductive material, and semiconductive material from between adjacent rows of pixels of the field emission array.
    Type: Grant
    Filed: July 6, 1999
    Date of Patent: September 26, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Ammar Derraa
  • Patent number: 6124150
    Abstract: A hybrid semiconductor package is formed from a die having two opposed elongate die edges with conductive bond pads arranged transversely relative to the rows of outer leads. A first portion of inner leads is off-die wire bonded to some of the bond pads, and a second portion of inner leads is insulatively attached as LOC leads between the bond pads along the opposed die edges. The hybrid package results in shorter inner leads of increased pitch enabling improved line yield at wire bond and encapsulation, as well as improved electrical performance, particularly for packages with very small dice.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: September 26, 2000
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 6123674
    Abstract: An airway valve, method of operation and ventilator circuit including the valve. The airway valve includes an outer housing defining a primary passage including first and second coaxial primary passage portions mutually directly communicating within the housing, and first and second diversion passages extending transversely to the primary passage, each diversion passage being integral with the housing and opening onto a primary passage portion. The airway valve controls diversion of air flow between the first primary passage portion and the second primary passage portion into and through an enlarged volume defined by a re-breathing loop external to the housing via the first and second diversion passages. To selectively effect such diversion, an elliptical valve element is oriented within the housing at a 45.degree. angle to both the first primary passage portion and the first diversion passage and disposed on the end of an actuation shaft aligned with the first diversion passage.
    Type: Grant
    Filed: October 15, 1998
    Date of Patent: September 26, 2000
    Assignee: NTC Technology Inc.
    Inventor: David R. Rich
  • Patent number: 6124565
    Abstract: A laser cutting machine includes a driving apparatus for moving a laser head axially. An inner sleeve having a converging lens is coupled to the laser head. An outer sleeve having a nozzle is supported to move relative to the inner sleeve. A braking mechanism is arranged between the inner and outer sleeves to selectively lock the outer sleeve to the inner sleeve. An actuator moves a catch to selectively engage the outer sleeve, which holds the outer sleeve at a predetermined position. The driving apparatus moves the laser head when the outer sleeve is held at the predetermined position and the outer sleeve is released from the inner sleeve by the braking mechanism. This moves the outer sleeve relative to the inner sleeve and automatically adjusts the distance between the converging lens and the nozzle. This permits automation of a focal point position adjustment method.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: September 26, 2000
    Assignee: Yamazaki Mazak Kabushiki Kaisha
    Inventors: Akio Morishita, Minoru Tashiro, Tetsuichi Kitamoto
  • Patent number: 6123160
    Abstract: A drill bit and method of drilling employing a gage definition region on the bit to relatively gradually and incrementally increase the diameter of the borehole being drilled from a diameter that is cut by fixed face cutters or rolling cone cutters on the bit body to a larger diameter. Preferably, the diameter of the gage definition region defined by cutting structures thereon varies along a longitudinal length of the bit, being smallest nearest the leading end of the bit. In a preferred embodiment, the gage definition region includes a plurality of helically arranged cutting elements disposed around the perimeter of the gage definition region. Such a configuration of cutting elements helps to reduce the loading on, and wear of, each individual cutting element. Thus the effective life of the bit is extended by enhancing its ability to drill the borehole to the gage diameter over a longer interval than may be achieved with conventional bit designs.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: September 26, 2000
    Assignee: Baker Hughes Incorporated
    Inventor: Gordon A. Tibbitts
  • Patent number: 6124634
    Abstract: A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: September 26, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, David R. Hembree, Warren M. Farnworth
  • Patent number: 6121070
    Abstract: A flip-chip semiconductor device comprises a carrier substrate having a conductor pattern on at least one side and at least one semiconductor die with an active surface and an opposed ground surface. A conductive backing plate is conductively bonded to the ground surface. The active surface faces and is electrically connected to the conductor pattern of the carrier substrate. A conductive down-bond connection is provided between the backing plate and a ground connection or reference potential connection. The backing plate is preferably rigid and can be manipulated for indirect alignment of the die or dice carried thereon relative to the substrate.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: September 19, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6120627
    Abstract: Technology for in situ remediation of undetonated explosive material. An explosive apparatus contains an explosive material in close proximity with microorganisms. An explosive mixture capable of self remediation in the form of an explosive material is intermixed with microorganisms. The microorganisms are either mobile or temporarily deactivated by freeze drying until rehydrated and remobilized. The microorganisms are capable of metabolizing the explosive material. Examples of such microorganisms include Pseudomonas spp., Escherichia spp., Morganella spp., Rhodococcus spp., Comamonas spp., and denitrifying microorganisms. A bioremediation apparatus that contains microorganisms and prevents contact between the microorganisms and explosive material is joined with an explosive apparatus that houses a charge of explosive material.
    Type: Grant
    Filed: October 18, 1996
    Date of Patent: September 19, 2000
    Assignee: The Ensign-Bickford Company
    Inventors: Farrell G. Badger, Brendan M. Welch, Ronald D. Thomas, Lyman G. Bahr, Dean F. Richards
  • Patent number: 6121067
    Abstract: A method for additively de-marking a packaged integrated circuit die bearing engraved marking indicia on an exterior surface thereof. The marked surface is covered with an overlayer of material to fill the engraved markings and provide a surface suitable for re-marking. The covering material may be applied in a flowable state by applicator contact or by non-contact dispensing, or may be applied as a preformed segment. The exterior surface to be covered may be pre-treated to enhance bonding of the covering material. The covering material may be bonded to the marked surface in a post-application curing operation. De-marked integrated circuit packages are also disclosed.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: September 19, 2000
    Assignee: Micron Electronics, Inc.
    Inventor: Robert L. Canella
  • Patent number: 6116974
    Abstract: A display device, and a method for making and operating the display device are described. The display device comprises a base plate containing at least one emitter, a display screen, and a spacer located between the base plate and display screen, where the spacer has a high concentration of an emitter-cleaning material. The spacer may comprise a xerogel or aerogel material and the emitter-cleaning material may comprise hydrogen. The spacer and a method for making the spacer and using the spacer to clean an emitter are also described. The spacer material cleans the emitter by absorbing gases during fabrication of the display device and desorbing emitter-cleaning gases during operation of the display device. By keeping the emitter clean, the spacer retains the work function of the emitter at a low level, thereby prolonging the usefulness of the display device.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Jim Browning, Surjit S. Chadha, deceased
  • Patent number: 6118291
    Abstract: A test socket for testing a vertical surface mount packaged semiconductor device, the test socket including a test substrate, a support member, and clamps. The test substrate includes terminals which are electrically connectable to a testing device. The shape of the support member is complementary to the shape of the bottom surface of leads extending from the vertical surface mount packaged semiconductor device. The shape of the clamps is complementary to the top surface of the leads. The test substrate may also define lead alignment notches around one or more of the terminals. Upon placement of a vertical surface mount packaged semiconductor device on the test substrate, the leads are aligned with their corresponding terminals, then placed against the terminals and the support member. The clamps are then placed against the leads, biasing each of the leads against the support member and its corresponding terminal.
    Type: Grant
    Filed: January 16, 1998
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Chris G. Martin, Manny Kin F. Ma
  • Patent number: 6118713
    Abstract: A DRAM is stress tested by writing a logic bit in a weakened state from a sense amplifier of the DRAM to a sub-array of the DRAM. This is accomplished by reducing an upper rail voltage supplied to a P-sense amp in the sense amplifier and increasing a lower rail voltage supplied to an N-sense amp in the sense amplifier, or by operating isolation NMOS transistors through which a differential voltage representative of the logic bit passes from the sense amplifier to the sub-array at less than a full activation level. Once the logic bit is written to the sub-array in a weakened state, it is then read back out to stress the DRAM and thereby identify weak sense amplifiers and DRAM cells in the DRAM.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventor: George B. Raad
  • Patent number: 6117793
    Abstract: A layered trace configuration comprising a conductive trace capped with a silicide material which allows for removal of oxide polymer residues forming in vias used for interlayer contacts in a multilayer semiconductor device and eliminates or greatly reduces the formation of metal polymer residues in the vias. The formation of an interlayer contact according to one embodiment of the present invention comprises providing a trace formed on a semiconductor substrate and a silicide layer capping the conductive layer. An interlayer dielectric is deposited over the silicide capped trace and the substrate. A via is etched through the interlayer dielectric, wherein the etch is selectively stopped on the silicide layer. Any residue forming in the via is removed and a conductive material is deposited in the via to form the interlayer contact.
    Type: Grant
    Filed: September 3, 1998
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Sanh D. Tang
  • Patent number: 6117382
    Abstract: The upper and lower mold plates of a transfer molding machine are configured for one-side encapsulation of a pair of substrate mounted electronic devices having an opposite conductor-grid-array and/or bare heat sink/dissipator. The pair of devices is positioned back-to-back within a single mold cavity for simultaneous encapsulation. A buffer member, optionally with cut-outs or apertures, may be placed between the two back-to-back substrates for protecting the grid-arrays and enabling encapsulation of devices with varying thicknesses without adjustment of the molding machine. Alternately, the upper and lower plates are configured for one-side encasement using covers of a pair of substrate mounted electronic devices having an opposite conductor-grid-array and/or bare heat sink/dissipator.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Steven G. Thummel
  • Patent number: 6116356
    Abstract: A method and apparatus for reaming or enlarging a borehole with enhanced stability. A pilot stabilization pad (PSP) having an axially and circumferentially tapered entry surface and a circumferential transition surface thereabove is employed to enhance the transition from the smaller diameter borehole to be enlarged while accommodating the side force vector generated by the cutting assembly used to effect the enlargement. In addition, one or more eccentric stabilizers are employed above the reaming apparatus to laterally or radially stabilize the bottomhole assembly, which may comprise either a straight-hole or steerable, motor-driven assembly.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: September 12, 2000
    Assignee: Baker Hughes Incorporated
    Inventors: Michael L. Doster, Rudolf C. O. Pessier, David M. Schnell, Bart T. McDonald
  • Patent number: 6117351
    Abstract: A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175.degree. C. and the second temperature may be about 155.degree. C.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: September 12, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Don L. Yates