Abstract: The present invention is directed to a page finder for a time management notebook such as a datebook, organizer or planner. The page finder comprises a body with a transparent cover partially affixed to it to form a pocket. An insert card having various role, goal and other personal information is inserted into the pocket. The page finder includes notches along the left side for removably attaching to the binder rings of the time management notebook. Accordingly, insert cards may be removably placed in the pocket, and the page finder may be selectively moved within the notebook to provide a user with ready access to the insert information adjacent to a current time page as the user plans records and reviews periodic activities.

Abstract: A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased position. After placement of the intermediate conductive elements into an insertion position, a semiconductor device may be inserted into a receptacle of the socket with minimal insertion force. Movement of the member to a biased position facilitates biasing of the intermediate conductive elements against a bond pad of the semiconductor device. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate. A first embodiment of the socket includes a member which moves transversely relative to the remainder of the socket. In a second embodiment of the socket, the member moves vertically relative to the socket body.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: Multi-chip module systems and method of fabrication thereof wherein the equivalent of a failed die of a multi-chip module (MCM) is added to the module in a vacancy position previously constructed with appropriate electrical connections. A variety of different dice may be attached to the same vacancy position of an MCM by means of adapters, wherein each adapter has the same footprint, but different adapters are capable of accommodating different numbers and types of dice.

Abstract: A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased position. After placement of the intermediate conductive elements into an insertion position, a semiconductor device may be inserted into a receptacle of the socket with minimal insertion force. Movement of the member to a biased position facilitates biasing of the intermediate conductive elements against a bond pad of the semiconductor device. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate. A first embodiment of the socket includes a member which moves transversely relative to the remainder of the socket. In a second embodiment of the socket, the member moves vertically relative to the socket body.

Abstract: There is a bi-level bit line architecture. Specifically, there is a DRAM memory cell and cell array that allows for six square feature area (6F.sup.2) cell sizes and avoids the signal to noise problems. Uniquely, the digit lines are designed to lie on top of each other like a double decker overpass road. Additionally, this design allows each digit line to be routed on both conductor layers, for equal lengths of the array, to provide balanced impedance. Now noise will appear as a common mode noise on both lines, and not as differential mode noise that would degrade the sensing operation. Furthermore, digit to digit coupling is nearly eliminated because of the twist design.

Abstract: A solder jet apparatus is disclosed. The solder jet apparatus is a continuous mode solder jet that includes a blanking system and raster scan system. The use of the raster scan and blanking systems allows for a continuous stream of solder to be placed anywhere on the surface in any desired X-Y plane. This allows for greater accuracy as well as greater product throughput. Additionally, with the raster scan system, repairs to existing soldered surfaces can be quickly and easily performed using a map of the defects for directing the solder to the defects.

Abstract: The present invention relates to an improve method for forming a UBM pad and solder bump connection for a flip chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

Abstract: An LOC die assembly including a die dielectrically adhered to the underside of a lead frame. The adhesive is applied over a minimum cross-sectional area and number of attachment points to maximize flexure of leads extending over the active surface of the die. In this manner, flexure of the leads to accommodate filler particles lodged between the leads and the active surface of the die during transfer molding of a plastic encapsulant is maximized, and the point stresses on the active surface caused by the filler particles are reduced by the lead flexure.

Abstract: A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process for the fully hermetic sealing of both sides and the edges of the semiconductor chip without the use of a separate package.

Abstract: An electrochemical reaction assembly and methods of inducing electrochemical reactions, such as for deposition of materials on semiconductor substrates. The assembly and method achieve a highly uniform thickness and composition of deposition material or uniform etching or polishing on the semiconductor substrates by retaining the semiconductor substrates on a cathode immersed in an appropriate reaction solution wherein a wire mesh anode rotates about the continuous moving cathode during electrochemical reaction.

Abstract: A ball grid array (BGA) package includes a central cavity for receiving a semiconductor die therein. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically-conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging.

Abstract: A method of forming elements for electrical and electronic devices, substrates, and other components from or including viscous material. The method includes inverting the electrical components after the viscous material is applied and maintaining the inverted orientation until the viscous material dries or cures enough to maintain definition of its perimeter and edge characteristics.

Abstract: An apparatus and method for increasing integrated circuit density comprising utilizing chips with both direct (flip chip type) chip to conductors connection technology and wire bonds and/or TAB. An aspect of the present invention comprises at least one semiconductor die with a face surface having both flip chip type electric connections and bond pads for wirebonding or TAB attachment thereof to at least one leadframe. Another aspect of the present invention comprises using two pair of back to back attached dice with leadframe lead fingers disposed between the dice pairs. The die face surfaces adjacent to the lead fingers are in direct electrical communication therewith via flip-chip type connectors. Bond pads on the die face surface facing outward from the lead fingers are electrically connected to the leadframe via wire bonds and/or TAB.

Abstract: In an inventive method for mapping the topography of an eye, elevation measurements of the eye are collected using a slit beam diffuse reflection system, such as an ORBSCAN.TM. device. An approximating b-spline surface is then fitted to the elevation measurements. Slope measurements of the eye are collected using a Placido-based reflective system, but the slope measurements are referenced to points on the b-spline surface, rather than to points approximated using the conventional constant curvature method, so the measurements have substantially improved accuracy. The elevation and slope measurements are then blended using weighted least squares fitting techniques. A new b-spline surface is fitted to the blended measurements, with the new surface having substantially improved accuracy in depicting the actual topography of the eye as a result of the elevation-improved accuracy of the slope measurements.

Abstract: This invention discloses a drilling structure having a body defining at least one primary channel and at least one secondary channel therein to initiate and maintain recirculation of an amount of drilling fluid back through the secondary channel to maintain positive, independent flow of drilling fluid through each primary channel of the drilling structure. The recirculation of drilling fluid is encouraged by providing a recirculation passageway in fluid communication with the primary channel defined by a portion of the body of the drilling structure that separates positively flowing drilling mud from drilling mud that is being recirculated. The recirculation action of the fluid in the recirculating loop may be fed and brought about by entrainment of the fluid with jetted fluid from an adjacent nozzle.

Abstract: This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe.sub.2).sub.4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening.

Abstract: A circuit and method provide isolated modulation of SRAM bitline voltage levels for improved voltage bump retention testing of the SRAM cells. A first FET is connected to Vcc, bitline load gates of the SRAM cell, and test mode operation control logic. A second FET is connected to the bitline load gates, the test mode logic, and an external pin of the SRAM device. During test mode operation, the first FET disables Vcc to the bitlines, and the second FET enables the internal bitline voltage levels to be modulated by a voltage supply received through the external pin of the device. Modulation of the bitline voltage levels is isolated from normal operating voltage levels of peripheral circuitry such as the wordlines. An alternate embodiment provides a CMOS transmission gate in place of the second FET.

Abstract: A DRAM memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible. The current limiting circuit comprises a long length, depletion mode transistor that has its gate voltage reduced when row-to-column shorts exist to limit the bleed current. An alternative embodiment uses a P-channel FET in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0.3 Volts.

Abstract: Antigenic substance or precursor thereof comprising a peptide part derived from an amino acid sequence located between two mucin-like regions of a protein G of a respiratory syncytial virus (RSV). Said andgenic substance or precursor thereof allows to discriminate between, or identify, different types or subtypes of respiratory syncytial viruses, or antibodies against them. In preferred embodiments, the peptide part is derived from protein G of bovine respiratory syncytial virus, human respiratory syncytial virus A, human respiratory syncytial virus B, or ovine respiratory syncytial virus. Use of the antigenic substance or precursor thereof (in vaccines) for prophylaxis of RSV infections, in assays and testkits for detecting or identifying (antibodies against) RSV types or subtypes, and in methods for obtaining antibodies against RSV types or subtypes. Use of such antibodies in assays and testkits for detecting or identifying RSV types or subtypes.