Abstract: A method for reducing the dynamic range required of an automatic gain control (AGC) circuit in a remote transceiver in 2-way communication between local and remote transceivers. By repeatedly transmitting a signal with successively increasing power from one transceiver until a response is received from the other transceiver, the dynamic range and hence complexity of the receiving circuit may be greatly reduced. The operating power of the remote transmitter can then be adjusted according to the level used by the local transmitter, thereby promoting the efficent use of the remote's power supply.

Abstract: A polycrystalline diamond layer attached to a cemented metal carbide structure used as a cutter in a drill bit wherein the cutter has improved toughness or fracture resistance during use through the inclusion of boron, beryllium or the like therein.

Abstract: An inventive method for sorting integrated circuit (IC) devices of the type having a substantially unique identification (ID) code, such as a fuse ID, includes automatically reading the ID code of each of the IC devices, and sorting the IC devices in accordance with their automatically read ID codes. The inventive method can be used in conjunction with an IC manufacturing process that includes providing semiconductor wafers, fabricating the IC's on each of the wafers, causing each of the IC's to store its ID code, separating each of the IC's from its wafer to form IC dice, assembling the IC dice into IC devices, and testing the IC devices.

Abstract: A semiconductor device, such as an integrated circuit die, includes a plurality of bond pads on an active surface thereof electrically connected to internal circuitry of the semiconductor device, and a plurality of jumper pads on the active surface which are electrically isolated from internal circuitry of the die. The jumper pads effectively provide stepping stones for wire bonds to be made across the active surface between bond pads. The jumper pads may be formed directly on the semiconductor device or on a non-conductive support structure that is attached to the semiconductor device.

Abstract: An apparatus for rinsing and drying semiconductor wafers. The apparatus includes side walls, end walls and a base. One embodiment of the apparatus includes a rigid side and end walls. In another embodiment of the apparatus, at least a portion of the side wall is collapsible. In yet another embodiment of the apparatus, at least a portion of the wall has a tambour configuration, facilitating bending or rolling of the wall beneath the base. The apparatus includes an assembly for injecting a rinse liquid into the chamber. The side walls, end walls, and base form a chamber configured to receive at least one semiconductor wafer. Rinse liquid can be directed into the chamber, over each semiconductor wafer therein to rinse each semiconductor wafer. At least a portion of a side wall can be lowered substantially vertically to permit rinse liquid to flow out of the chamber. The apparatus also includes an assembly for injecting a drying fluid into the chamber.

Abstract: A first adhesively coated tape material length is supplied to a first die associated with a cutting and application mechanism. A second length of adhesively coated tape material is also provided to a second die of the cutting and application mechanism. A plurality of LOC leadframes is supplied sequentially through the application structure to apply a first decal cut from the first tape material to a first die site at a first location and to apply a second decal cut from the second tape material to a second die site at a second location.

Abstract: A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a first layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the first layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers.

Abstract: This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG..

Abstract: A semiconductor integrated circuit device, and method of manufacturing the same, having a conventional-type lead frame with the die paddle removed. In particular, the die paddle is replaced with a section of tape that is supported by the ends of the lead fingers. The semiconductor die is attached to the tape so that it may be wire bonded to the lead fingers. The tape contains at least one slot to allow for expansion and/or contraction of the tape due to various temperatures experienced during the manufacturing process so that the tape does not wrinkle or warp to alter the position of the die.

Abstract: A multi-chip module (MCM) and method of manufacturing is disclosed that provides for attachment of semiconductor dice to both sides of the MCM printed circuit board (PCB). Semiconductor dice attached to the top surface of the PCB may be attached by conventional wire bonding, TAB or flip chip methods whereas those semiconductor dice attached to the bottom surface of the PCB are wire bonded or TAB connected to the top surface through openings in the PCB. The openings provide a lead-over-chip (LOC) arrangement for those semiconductor dice attached to the bottom surface, resulting in shortened wire bonds. The bottom surface of the PCB may be provided with die recesses into which the openings extend to receive the dice and bring their active surfaces even closer to the top surface of the PCB for wire bonding.

Abstract: A modular bare die socket assembly 10 for attaching a plurality of miniature semiconductor dice 18 to a substrate. The socket assembly 10 is comprised of a plurality of two-sided plates 14 joined vertically in a horizontal stack, wherein each plate 14 has a die socket 22 for the removable insertion of a bare semiconductor die 18. A multi-layer interconnect lead tape 50 has a plurality of lithographically formed leads bent on one end to form nodes 88 for attachment to bond pads 90 on the removably inserted semiconductor die 18, and having opposing ends 92 connectable to the substrate.

Abstract: An LOC die assembly is disclosed including a die dielectrically adhered to the underside of a lead frame. An underfill material is introduced between each lead finger and semiconductor die, extending from the bonding location of the die and the edge of the die, in order to prevent filler particles from lodging between the leads and the active surface of the die during transfer molding of a plastic encapsulant. The seal created by the underfill material reduces point stresses on the active surface of the die usually caused by the filler particles. The decreased flexure in the leads further enhances the locking of the leads in position with respect to the die.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A semiconductor device including bond pads disposed proximate an edge thereof, and an overcoat layer. The overcoat layer defines notches around each of the bond pads. The overcoat layer may be formed from a photoimageable material such as a photoimageable epoxy. The invention also includes an alignment device that secures the semiconductor device perpendicularly upon a carrier substrate. The alignment device includes intermediate conductive elements which correspond to the bond pads of the semiconductor device. Upon insertion of the semiconductor device into the alignment device, the notches facilitate alignment of the bond pads with their corresponding intermediate conductive elements. The intermediate conductive elements establish an electrical connection between the semiconductor device and the carrier substrate.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical test equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical test are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: A method of manufacturing a drill bit or other drilling-related structure used for drilling into subterranean formations is herein disclosed where a blank is formed by placing a ferrous metal powder such as steel into a mold, sintering the ferrous metal powder to form a preformed blank, packing an abrasion- and erosion-resistant material such as tungsten carbide powder around the preformed blank, and infiltrating the preformed blank and tungsten carbide with a common binder such as a copperbased binder. For some materials, during sintering, the preformed blank may shrink in size relative to the mold enough to provide space between the mold and the preformed blank for a layer of abrasion- and erosion-resistant material. With other materials, a separate blank mold may be used to form the sintered blank which can then be inserted into the mold for infiltration.

Abstract: A vascular access port enclosing a pair of distinct fluid reservoirs includes a two-piece housing that captures an integrally-formed compound septum to seal both of the fluid reservoirs for selective access with a hypodermic needle. The housing includes a base that defines the fluid reservoirs and a cap in which the base is received with the compound septum therebetween. The compound septum includes two distinct target domes that are exposed to the exterior of the housing through respective access apertures in the cap, when the compound septum is captured in the housing. A planar septum web interconnects and encircles the target domes. The side of the septum web opposite from the target domes is formed into a recessed isolation groove that traverses the septum web between the target domes. Sealing ridges depend from this side of the septum web on either side of the isolation groove. The outlet stem of the access port is integrally formed with the base of the housing.

Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.

Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.