Patents Represented by Attorney Trop, Pruner & Hu, P.C.

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  • Transferring architectural functions of a processor to a platform control hub responsive to the processor entering a deep sleep state
    Patent number: 8230247
    Abstract: Power consumption and dissipation during sleep states of processors is reduced using a novel connected standby sleep state. In the connected standby sleep state a dedicated power plane is used to maintain processor context. To conserve power, unnecessary components on the processor are powered down, including all of the clock components, and wakeup sources previously directed to the processor are directed to a platform control hub. The platform control hub sustains certain architectural functions for the processor during connected standby sleep state, and manages the wakeup logic for returning the processor to the preceding sleep state.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventor: Jawad Haj-Yihia
  • Embedding thin film resistors in substrates in power delivery networks
    Patent number: 8228680
    Abstract: Using die side capacitors and embedded resistors, an advantageous power delivery network may be achieved. In some embodiments, the embedded resistors may be more precisely controllable. The number of die side capacitors may be reduced by combining embedded resistors with these capacitors to reduce costs. The embedded resistors may be provided within the metallization layers either at an upper layer or a lower layer, as two examples.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Myitzu Soe Myat, Mooi Ling Chang, Eu Soon Lee, Yongki Min, King Keong Wong
  • Reducing artifacts as a result of video de-interlacing
    Patent number: 8228429
    Abstract: In accordance with some embodiments of the present invention, de-interlacing may be accomplished by using an edge gradient to select a best interpolation direction for several adjacent pixels between two lines of interlaced video. The interpolation of the intermediate line is performed using the best direction. Then the pixels in the line above and below are analyzed to determine whether the interpolated pixel value should actually be used in view of the possible presence of artifacts.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Tiehan Lu, Chunjuan Liu
  • Booting an operating system of a system using a read ahead technique
    Patent number: 8230208
    Abstract: In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventor: Adriaan Van De Ven
  • Real-time interactive personal video recorder interface
    Patent number: 8230476
    Abstract: Interacting with a television program includes beginning playback of the program for perception by a user, analyzing the program to detect a cue within the program, automatically pausing playback of the program when the cue is detected, accepting user input data in response to the cue, resuming playback of the program when the user input data is received, and comparing the user input data to a non-user response. Interactivity provided by the program analysis, pausing playback, accepting user input data, resuming playback, and comparing operations supports execution of at least one of an entertainment application and an educational application at a user's site without requiring modification of the television program by a program provider.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventor: Dave P. Singh
  • Adaptive wordline programming bias of a phase change memory
    Patent number: 8228723
    Abstract: The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied to the bitline of a programmed cell, the word lines of unselected cells may vary correspondingly. In some embodiments, the word line voltage may be caused to match the bitline voltage of the programmed cell.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Richard E. Fackenthal, Ferdinando Bedeschi, Meenatchi Jagasivamani, Ravi Annavajjhala, Enzo M. Donze
  • Pre-boot environment power management
    Patent number: 8230237
    Abstract: A pre-boot environment is disclosed that manages power of a computing device prior to an operating system runtime phase. The pre-boot environment may be implemented in a computing device having a storage device to store an operating system, a firmware device to store firmware having a boot loader to load and initiate execution of the operating system, and a processor to execute the firmware and the operating system. The firmware in response to being executed by the processor may result in the computing device monitoring operating conditions of the computing device, and initiating a power management response based upon the operating conditions of the computing device and a power management policy.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Jiewen Yao, Hua Shao
  • Reducing temporal changes in phase change memories
    Patent number: 8228722
    Abstract: A phase change memory in the reset state may be heated to reduce or eliminate electrical drift.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Semyon D. Savransky, Ilya V. Karpov
  • Detecting spin loops in a virtual machine environment
    Patent number: 8230203
    Abstract: Embodiments of apparatuses, methods, and systems detecting spin loops in a virtual machine environment are disclosed. In one embodiment, an apparatus includes detection logic and virtualization logic. The detection logic is to detect whether a guest is executing a spin loop. The virtualization logic is to transfer control of the apparatus from the guest to a host in response to the detection logic detecting that the guest is executing the spin loop.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Randolph L. Campbell, James B. Crossland, Gideon Gerzon, Leena K. Puthiyedath, Stephen A. Fischer, Steven M. Bennett, Andrew V. Anderson
  • Dynamic allocation of a buffer across multiple clients in a threaded processor
    Patent number: 8225012
    Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.
    Type: Grant
    Filed: September 3, 2009
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventor: Thomas A. Piazza
  • Semiconductor phast change memory using multiple phase change layers
    Patent number: 8223538
    Abstract: In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. For example, in one embodiment, a diffusion barrier layer may be maintained between the two distinct phase change layers. In another embodiment, a face centered cubic chalcogenide structure may be utilized.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: July 17, 2012
    Assignee: Ovonyx, Inc.
    Inventors: Charles H. Dennison, Stephen J. Hudgens
  • Pre-charging an inverter using an auxiliary winding
    Patent number: 8223515
    Abstract: A transformer module includes a main primary winding coupled to a first input power source to receive a medium voltage signal, multiple main secondary windings each to couple to a power cell of a drive system, and an auxiliary primary winding coupled to a second input power source to receive a low voltage signal. The auxiliary primary winding can be spatially separated from the main windings to increase leakage inductance. The auxiliary primary winding can be active during a pre-charge operation to pre-charge the power cells.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: July 17, 2012
    Assignee: TECO—Westinghouse Motor Company
    Inventors: Mehdi Abolhassani, Thomas Keister, Alex Skorcz, Ryan Edwards, Enrique Ledezma
  • Performing a cyclic redundancy checksum operation responsive to a user-level instruction
    Patent number: 8225184
    Abstract: In one embodiment, the present invention includes a method for receiving a user-level instruction for a checksum operation in a processor, where the user-level instruction specifies a source operand of a first size and a destination operand of a second size, receiving the source operand and the destination operand in the processor, and performing the checksum operation using the source operand and the destination operand in the processor responsive to the instruction. In an embodiment, the processor has multiple hardware engines that each can perform the checksum operation for one of multiple data sizes. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventors: Steven R. King, Frank Berry, Michael E. Kounavis
  • Method and apparatus for symbol synchronization for an 802.15.4 radio platform
    Patent number: 8223820
    Abstract: A technique for receiving a data stream including a spreading sequence packet of information containing a data payload and, in addition to the data payload, packet overhead including at least periodic information and at least one unique section of known coded information that defines a unique position within the packet, includes performing a plurality of processing steps to detect the position of the unique section within the packet of information. The steps include detecting the periodicity of the periodic information in a first processing step; in a second processing step after periodicity in the received data stream has been determined, estimating the position of the unique section within the packet of information; and in a third processing step, correlating the information in the packet of information about the estimated position with the known coded information.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: July 17, 2012
    Assignee: Silicon Laboratories Inc.
    Inventor: Alexandre Rouxel
  • Scheme for securing locally generated data with authenticated write operations
    Patent number: 8219829
    Abstract: A scheme for securing a locally generated data on a system using authenticated write operations is disclosed. According to an embodiment of the present invention, a private/public key pair is randomized and repeatedly generated to protect operations to data blocks.
    Type: Grant
    Filed: December 8, 2005
    Date of Patent: July 10, 2012
    Assignee: Intel Corporation
    Inventor: John Rudelic
  • Topology hiding of a network for an administrative interface between networks
    Patent number: 8218459
    Abstract: An administrative interface is provided between a first network and a second network, where the administrative interface is separate from one or more communications session signaling interfaces between the first network and second network. At least one of authorization, authentication, and accounting messages is communicated over the administrative interface. A module associated with the administrative interface is provided to perform topology hiding of the first network such that topology information of the first network is hidden from the second network.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 10, 2012
    Assignee: Genbrand US LLC
    Inventor: Brian Stucker
  • Generating a process and temperature tracking bias voltage
    Patent number: 8219049
    Abstract: In one embodiment, a method includes generating a current that is proportional to a mobility and an oxide capacitance of a tracking device and independent of a threshold voltage variation of the tracking device, generating a voltage from the current, and providing the voltage as at least part of a bias voltage for another device. In one embodiment, this other device may be a compensation circuit coupled to a main device to compensate for capacitance non-linearity of the main device.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: July 10, 2012
    Assignee: Javelin Semiconductor, Inc.
    Inventors: Anil Samavedam, David E. Bockelman, Vishnu Srinivasan
  • Managing timing of a protocol stack
    Patent number: 8218580
    Abstract: A method includes receiving a communication in a protocol stack coupled to a tunneling interconnect, determining whether a communication type is subject to altered timing to accommodate a delay associated with the tunneling interconnect, adjusting a timing of at least one stack logic to accommodate the delay, and handling the communication using the adjusted timing. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: July 10, 2012
    Assignee: Intel Corporation
    Inventor: David J. Harriman
  • Subdividing geometry images in graphics hardware
    Patent number: 8217942
    Abstract: A system may include a graphics memory, a data bus, a processor, and a vertex shader. The data bus may be operatively connected to the graphics memory. The processor may send vertex data to the graphics memory via the data bus. The vertex shader may read the vertex data from the graphics memory and may subdivide the vertex data into subdivided vertex data. The vertex shader may also write the subdivided vertex data to the graphics memory.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: July 10, 2012
    Assignee: Intel Corporation
    Inventors: Adam T. Lake, Carl S. Marshall
  • Partial regeneration in a multi-level power inverter
    Patent number: 8213198
    Abstract: In one embodiment, the present invention includes a medium voltage drive system having multiple power cells each to couple between a transformer and a load. A first subset of the power cells are configured to provide power to the load and to perform partial regeneration from the load, and a second subset of the power cells are configured to provide power to the load but not perform partial regeneration. A controller may be included in the system to simultaneously control a DC bus voltage of at least one of the first subset of the power cells, correct a power factor of the system, and provide harmonic current compensation for the system.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: July 3, 2012
    Assignee: TECO-Westinghouse Motor Company
    Inventors: Mehdi Abolhassani, Thomas Keister, Alex Skorcz, Enrique Ledezma, Ryan Edwards