Abstract: In one embodiment, the present invention includes a method for constructing a data dependency graph (DDG) for a loop to be transformed, performing statement shifting to transform the loop into a first transformed loop according to at least one of first and second algorithms, performing unimodular and echelon transformations of a selected one of the first or second transformed loops, partitioning the selected transformed loop to obtain maximum outer level parallelism (MOLP), and partitioning the selected transformed loop into multiple sub-loops. Other embodiments are described and claimed.

Abstract: In one embodiment, a gain medium for an external cavity diode laser (ECDL) includes a gain section to provide a gain operation on optical energy in the ECDL that is controlled by a first electrical signal, a semiconductor optical amplifier (SOA) section disposed adjacent to the gain section to amplify the gained optical energy responsive to a second electrical signal, and a trench disposed between the gain section and the SOA section to act as an integrated mirror. Other embodiments are described and claimed.

Abstract: A method, computer system, and computer-readable medium with instructions to provide a client security management layer and a content player that ensure that the content is protected from malware on the receiving computer system. The client security management layer controls access to a protected portion of a memory of a computer system on behalf of a component, such as the content player, running on the processor of the computer system. The client security management layer receives an encrypted content key from the component, confirms the integrity of the component, decrypts the encrypted content key to provide a decrypted content key, and places the decrypted content key in the protected portion of the memory in response to confirming the integrity of the component. Other embodiments are described and claimed.

Abstract: A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect.

Abstract: Embodiments of apparatuses and methods for improving performance in a virtualization architecture are disclosed. In one embodiment, an apparatus includes a processor and a processor abstraction layer. The processor abstraction layer includes instructions that, when executed by the processor, support techniques to improve the performance of the apparatus in a virtualization architecture.

Abstract: In one embodiment, the present invention includes a pre-driver to receive data of a first clock phase and to pre-drive the data, a driver coupled to the pre-driver to drive the data onto a link operable to be coupled to a receiver, and an offset driver to drive an offset value associated with the first clock phase onto the link with the data. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: A video decoder cache used for motion compensation data may be dynamically reconfigured. In some embodiments, it may be reconfigured on picture or frame boundaries and in other embodiments it can be reconfigured on sequence boundaries. The cache may be flushed on each boundary to enable such reconfiguration.

Abstract: Apparatus, systems and methods for the simplification of 3D texture address computations based on aligned, non-perspective objects are disclosed. For example, a method is disclosed including receiving a texture address of a first pixel and determining a texture address of a second pixel by applying at least one offset to the texture address of the first pixel. Other implementations are also disclosed.

Abstract: When a processing system boots, it may retrieve an encrypted version of a cryptographic key from nonvolatile memory to a processing unit, which may decrypt the cryptographic key. The processing system may also retrieve a predetermined authentication code for software of the processing system, and the processing system may use the cryptographic key to compute a current authentication code for the software. The processing system may then determine whether the software should be trusted, by comparing the predetermined authentication code with the current authentication code. In various embodiments, the processing unit may use a key stored in nonvolatile storage of the processing unit to decrypt the encrypted version of the cryptographic key, a hashed message authentication code (HMAC) may be used as the authentication code, and/or the software to be authenticated may be boot firmware, a virtual machine monitor (VMM), or other software. Other embodiments are described and claimed.

Abstract: A video system includes an analyzer and a bit depth predictor. The analyzer receives a first coded video signal, which is indicative of first values for pixels. The first values are associated with a first bit depth. The analyzer, for each pixel, analyzes the first values for the pixels located in a neighborhood that contains said each pixel. The bit depth predictor, based at least in part on the analysis, generates a second coded video signal that is indicative of second values for the pixels. The second values are associated with a second bit depth that is different than the first bit depth.

Abstract: In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed.

Abstract: The present invention provides an apparatus for transferring data through an electromagnetic coupler. The apparatus comprises a transmitter to encode a first plurality of bits into a symbol, a receiver to decode a transferred symbol into a second plurality of bits; and a coupling element having a geometry that provides robust electromagnetic transfer of the symbol and the transferred symbol. For one embodiment of the apparatus, the coupling element has a zig-zag geometry.

Abstract: In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer, generating a mapping of which second clocks of the reader that the reader is allowed to read from the queue, based at least in part on the first and second clocks, and reading the data from the entry at an allowed second clock. Other embodiments are described and claimed.

Abstract: Embodiments of apparatuses, methods, and systems for decoding a virtual machine control structure identification are disclosed. In one embodiment, an apparatus includes a virtual machine control structure to decode a virtual machine control structure identification data. The virtual machine control structure identification data is decoded into an address of a virtual machine control structure field and an offset. The offset is to help identify a micro-operation associated with a virtual machine architecture instruction to be executed.

Abstract: A technique includes converting a first value for a pixel that is associated with a lower bit depth into a second value for the pixel, which is associated with a higher bit depth based at least in part on a neighborhood of the pixel.

Abstract: In one embodiment, the present invention includes an amplifier having an input to receive a radio frequency (RF) signal from an output node of a source. An input stage coupled to the amplifier input may include one or more components to aid in processing of incoming signals. One such component coupled between the source and the input of the amplifier is a coupling capacitor used to maintain a bias voltage of the amplifier at a different potential than a DC voltage of the output node. In certain applications, the amplifier and the coupling capacitor may be integrated on a single substrate.

Abstract: A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

Abstract: Embodiments of the invention provide assigning two different class identifiers to a device to allow loading to an operating system as different devices. The device may be a graphics device. The graphics device may be integrated in various configurations, including but not limited to a central processing unit, chipset and so forth. The processor or chipset may be associated with a first identifier associated with a graphics processor and a second device identifier that enables the processor or chipset as a co-processor.

Abstract: In one embodiment, the present invention includes a method for obtaining a pre-boot authentication (PBA) image from a full disk encryption disk in a pre-boot environment, executing the PBA using a chipset to obtain user credential information, authorizing the user based on the user credential information and stored credential information, and storing the user credential information in a PBA metadata region of the disk. Other embodiments are described and claimed.