Abstract: The present disclosure relates to methods and apparatus for controlling power consumption of a plug-in card or circuit module. The disclosed method, in particular, controls power to a circuit module and includes implementing a user interface and power manager to automatically control the power state of the circuit module by, among other things, powering the module up or down using a simulated hot unplug of the device. The apparatus further includes use of an I/O interconnect to allow the system BIOS to simulate the hot unplugging of the module.

Abstract: The present application discloses a method for communicating between at least two different levels of software components. The method includes establishing a command set common to the at least two different levels of software components. Additionally, the method includes providing a command decoder operable by both of the at least two levels of software components, the command decoder configured to decode the command set. By providing a common command set between different levels of software components, such as a software driver and a BIOS, where the commands within the command table are interpreted and executed by an identical command decoder that interprets and executes the same command tables, this ensures that the same features or functions are implemented or executed in the same way across different levels of the software components. Accordingly, redundant implementation of the same functions by different software components is eliminated.

Abstract: A direct digital synthesis circuit (108) includes a plurality of current sources (210, 211, 212), an output circuit (200), and a logical multiplier circuit (202). The output circuit (200) provides a synthesized waveform (164) output and includes a first (206) and second branch (208). The logical multiplier circuit (202) is operatively coupled to the plurality of current sources (210, 211, 212) and to the output circuit (200). The logical multiplier circuit (202) is operative to receive a plurality of signals. The logical multiplier circuit is also operative to selectively increase a first current flow through the first branch (206) by a determined magnitude and decrease a second current flow through the second branch (208) by the determined magnitude based on the plurality of signals. The synthesized waveform (164) is based on the first and second currents.

Abstract: A 6-pin electronic package includes a first side including a pair of first outer pins and a first middle pin, and a second side including a pair of second outer pins and a second middle pin. The first outer pins and the second middle pin are operatively coupled to a first circuit to provide a first function. The second outer pins and the first middle pin are operatively coupled to a second circuit to provide a second function. The 6-pin electronic package can be replaced on a circuit substrate with a first electronic package and a second electronic package that collectively include at least six pins. The 6-pin electronic package and the first and second electronic packages can be interchangeably used on a circuit substrate of an electronic device. The circuit substrate may include any one of the 6-pin electronic package mountable to the circuit substrate, and the first and second electronic packages.

Abstract: A scan flip-flop circuit including a data input, a scan input, a data output, a flip-flop, a multiplexer and a delay element is provided. The multiplexer allows selection of either the scan input or the data input for presentation at the input of the flip-flop. The flip-flop provides an output signal at the output of the scan flip-flop. The delay element is in a signal path between the scan input and the input of the flip-flop, and provides a signal propagation delay between the scan input and the input of the flip-flop. The delay between the scan input and the input of the flip-flop is substantially larger than the signal propagation delay between the data input and the input of the flip-flop. The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.

Abstract: Conventional heat bonding and anodic bonding require heating at high temperature and for a long time, leading to poor production efficiency and occurrence of a warp due to a difference in thermal expansion, resulting in a defective device. Such a problem is solved. An upper wafer 7 made of glass and a lower wafer 8 made of Si are surface-activated using an energy wave before performing anodic bonding, thereby performing bonding at low temperature and increasing a bonding strength. In addition, preliminary bonding due to surface activation is performed before main bonding due to anodic bonding is performed in a separate step or device, thereby increasing production efficiency, and enabling bonding of a three-layer structure without occurrence of a warp.

Abstract: Embodiments of the present invention are directed to a method and apparatus for block based image compression with multiple non-uniform block encodings. In one embodiment, an image is divided into blocks of pixels. In one embodiment the blocks are four pixels by four pixels, but other block sizes are used in other embodiments. In one embodiment, a block of pixels in the original image is compressed using two different methods to produce a first and second compressed block. Thus, each block in the original image is represented by two, typically different, compressed blocks. In one embodiment, color associated with a pixel is determined by combining the compressed information about the pixel in the first compressed block with information about the pixel in the second compressed block. In another embodiment, global information about the image is combined with the information in the first and second compressed blocks.

Abstract: A tray denesting apparatus is provided comprising a receptacle for holding at least one nested stack of packing trays. A conveyer belt is further provided for receiving each of the packing trays upon release from the receptacle. The denesting apparatus has at least one set of soft flexible suction cups disposed below the conveyer belt and which are disposed on a bellows assembly which is moveable between a first position and a second position so that at least one of the soft flexible suction cups may adhere to a first one of the packing trays, and successive packing trays. The tray denester further may include an automatic adjustment apparatus to correspond with selected size parameters of the trays being utilized. As a result, an individual tray may be removed from the receptacle, deposited on the conveyer belt and the conveyer belt then advancing the selected tray to the required area of use.

Abstract: A wireless mobile terminal (10) and method for utilizing digital broadcast content records (204) selected digital broadcast content as received, for example, by a digital broadcast receiver (16) and provides editing of the selected digital broadcast content based on digital rights management data to generate customized clips of information. The selected digital broadcast content is edited (206) to produce mobile terminal edited digital broadcast content that may be, for example, distributed (208) by the mobile terminal to a plurality of peer devices. A broadcast content editor (24) allows for the editing of clips of content wherein the edited clips are then stored in memory as recorded clips for distribution by the mobile terminal. In another embodiment, a network element is remotely controlled by the mobile terminal to effect editing through the mobile terminal at the network element.

Abstract: In one aspect of the present invention, a device for sensing an absolute position of an encoded object, comprising: a position tracking module comprising: a track illumination module configured to illuminate the encoded object with one more light beams, and to detect one or more light beams resulting from said illumination of said encoded object; and an absolute position determinator configured to determine the absolute position of the encoded object based on said one or more light beams resulting from said illumination of said encoded object.

Abstract: A hardware tessellation circuit serves as a unified hardware parametric coordinate generator for providing parametric coordinates for tessellation. The tessellation circuit includes control logic that receives tessellation instruction information, such as an instruction indicating which type of multiple tessellation operations to perform, on an incoming primitive wherein the different types of tessellation include discrete tessellation, continuous tessellation and adaptive tessellation. The tessellation circuit also includes shared tessellation logic that is controlled by the control logic, and includes a plurality of shared logic units, such as arithmetic logic units, that are controllable by the control logic based on the type of tessellation detected to be used for the incoming primitive. The shared tessellation logic is controlled to reuse at least some of the logic units for two different tessellation operations defined by the tessellation type information.

Abstract: A method for rendering an object including receiving a pixel tile representing a portion of a primitive to be rendered, determining attributes of a reference pixel within the pixel tile, and determining the attributes of neighboring pixels within the pixel tile based on barycentric differences relative to the reference pixel is disclosed. A circuit for calculating at least one attribute of an object to be rendered includes an initial calculation circuit providing full precision reference pixel attribute data in response to a pixel tile that defines at least a portion of the object; and a derivative circuit, operatively coupled to the initial calculation circuit, providing reduced precision neighboring pixel attribute data in response to the pixel tile. The derivative circuit includes a plurality of pixel attribute sub-circuits or components, which determine the attribute values of neighboring pixels within the pixel tile at a precision less than that of the precision used to define the reference pixel.

Abstract: An air drying system using plural air drying units. The system includes moist air and dry air plenums and a pair of substantially identical air drying canisters. Each unit has a single lower bases and a single, flanged mounting bracket. The moist air plenum is connected to an air inlet in the lower base, and the dry air plenum is connected to a dry air outlet in the lower base.

Abstract: Disclosed are enriched preparations of neuroblastoma tumor initiating cells (NB TICs). The NB TICs are capable of self-renewal, initiating neuroblastoma tumor growth in vivo and are capable of being passaged in high frequency. These NB TICs have chromosomal abnormalities and are capable of giving rise to secondary tumor spheres. Methods are also disclosed for preparing the enriched preparations of NB TICs, such as from neuroblastoma tumor tissue and metastasized bone marrow. Also disclosed are methods of screening candidate substances to identify therapeutic agents for the treatment of neuroblastoma. Methods are also provided for screening a sample for neuroblastoma, as well as for screening a sample to identify the stage of neuroblastoma present. Kits are also provided for selecting appropriate anti-neuroblastoma compounds for a patient, and utilize isolated compositions of the patients' neuroblastoma tumor initiating cells. In this manner, a customized medicinal profile for the patient may be devised.

Abstract: A method of manufacturing armature windings for an electro-mechanical machine, includes manufacturing a band of conductor elements with at least one layer, formation of windings on a tool and installation of the windings into an armature. The method results in a highly uniform winding, increased fill percentage in slots, improved electrical efficiency, lower material cost and labor consumption for manufacturing and complete automation of production.

Abstract: The present invention relates to a parallel pipeline graphics system. The parallel pipeline graphics system includes a back-end configured to receive primitives and combinations of primitives (i.e., geometry) and process the geometry to produce values to place in a frame buffer for rendering on screen. Unlike prior single pipeline implementation, some embodiments use two or four parallel pipelines, though other configurations having 2^n pipelines may be used. When geometry data is sent to the back-end, it is divided up and provided to one of the parallel pipelines. Each pipeline is a component of a raster back-end, where the display screen is divided into tiles and a defined portion of the screen is sent through a pipeline that owns that portion of the screen's tiles. In one embodiment, each pipeline comprises a scan converter, a hierarchical-Z unit, a z buffer logic, a rasterizer, a shader, and a color buffer logic.

Abstract: An apparatus and method for image rendering includes a first buffer operative to receive first video data. A motion mad updater receives video data from the first buffer and updates a motion map using the first video data. A grain information generator is coupled to the first buffer and receives the first video data to generate slope information based on the first video data. A grain information filter receives the slope information and filters the slope information to generate filtered slope information. A spatially interpolated field generator receives the filtered slope information and generates a spatially interpolated field. A maximum difference value generator generates a maximum difference value based on the update motion map. A base value generator receives the first video data and the spatially interpolated field and generates a base value therefrom. A missing video data generator generates missing first video data.

Abstract: Structures, subassemblies, devices, systems, and subsystems selected from: (1) a unitary holographic drive head assembly mounting structure; (2) an assembly including a unitary holographic drive head assembly mounting structure and a plurality of holographic drive head components and/or subassemblies; (3) a subassembly including a spatial light modulator, detector array, and a beam splitter; (4) a device including a spatial light modulator and a physical aperture positioned over or an imaged aperture projected onto the photoactive area of the spatial light modulator; (5) a system for optically aligning or pointing a laser in a holographic drive head assembly; (6) a light source subassembly including a laser, a fiber coupling lens; and an optical fiber having a fiber connector ready output end; and (7) a light source subsystem including a laser source, beam conditioning optics, fiber coupling optics for receiving the conditioned light beam, and a fiber optic connector for receiving the conditioned light beam f

Abstract: A signal integrator and method for integrating a continuous current and a discrete charge in which the discrete charge is provided for integration during multiple overlapping time intervals.