Abstract: There is provided a method of dechucking from an electrostatic chuck a substrate held by one or more residual forces to the chuck, the method comprising the steps of: (a) reducing a residual chucking force due to the electrostatic chuck polarisation; (b) contracting the chuck with the substrate attached thereto with a plasma for a time sufficient substantially to remove any residual charge from the surface of the substrate and the chuck; and (c) subsequently to, or simultaneously with, step (b) removing the substrate from the chuck. Also disclosed is an apparatus for performing the method.

Abstract: A metrology system and method uses pulsed light to allow continuous movement of a target relative to the sensor. A metrology system and method uses dynamic adjustment of tilt in a system. A metrology system and method calibrates the system to remove inherent optical aberrations in the system. Filtering may also be used in the system to increase accuracy.

Abstract: A method for removing contaminant compounds respectively having a benzene ring therein from the surface of an Si layer, the method containing enter a step for causing the Si layer to contact with the air, oxygen or ozone under a heated condition or a step for causing the Si layer to contact with a mixture of sulfuric acid and hydrogen peroxide or a mixture of pure water and ozone. The method can be applicable to methods for providing a field effect transistor.

Abstract: A chemical vapor deposition (CVD) method for depositing a suicide and a CVD system for performing the same are disclosed. A silicide is deposited on a substrate. Residual gases remaining from the depositing step are purged out by flowing air including H2O (g), to substantially remove fumes caused by the residual gases. In the purge step, the cycle purge is carried out at the conditions similar to the flow of atmosphere, to substantially remove the fumes.

Abstract: An apparatus for processing a semiconductor wafer has a circular chuck and a focus ring. The chuck is located in a process chamber and holds the semiconductor wafer. The focus ring surrounds the semiconductor wafer held by the chuck and focuses processing gases or plasma on a surface of the semiconductor wafer. The focus ring has a stepped inner periphery formed by a cylindrical lower surface surrounding the wafer and having a first diameter, a cylindrical upper surface having a second diameter greater than the first diameter, and a collector interposed between the lower surface and the upper surface for collecting contaminants created at the upper surface due to a reaction between the processing media and the material of the focus ring. The collector collects particulate contaminants falling from the upper surface of the focus ring so that the contaminants do not reach the wafer.

Abstract: A word-line driving circuit drives the word lines of a non-volatile semiconductor memory to different potentials to read, write, and erase data in memory cells coupled to the word lines. A ground potential is supplied to non-driven word lines through respective switching elements. The data in the memory cells coupled to some or all of the word lines can be erased simultaneously by driving those word lines to an erasing potential. When this is done, a mitigating potential intermediate between the ground potential and the erasing potential is supplied to the switching elements of the driven word lines, thereby reducing current leakage through these switching elements, which are switched off.

Abstract: A delay line receives an input clock signal and includes a cascaded plurality of unit delay circuits. A mode register set stores a value indicative of a column-address-strobe (CAS) latency of the memory device, and an adjustment circuit varies a delay time of the unit delay circuits according to the CAS latency stored in the mode register set. A phase detector detects a phase difference between the input clock signal and an output clock signal of the delay line, and a control circuit which controls an enabled state of the unit delay circuits according to an output of said phase detector.

Abstract: A method of fabricating a flash memory device uses a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating layer pattern such that the conductive layer and the oxidation-blocking layer conform to the stepped pattern. A photoresist layer is formed on the oxidation-blocking layer such that the photoresist layer has an upper surface situated above the oxidation-blocking layer. A portion of the photoresist layer is dissolved, without having photo-exposed the photoresist layer, by soaking the photoresist layer in developing solution. This soaking alone, or supplemented with an etch back process, is carried out until the upper surface of the photoresist layer is situated below the upper surface of the oxidation-blocking layer on the stepped pattern. The resulting photoresist pattern exposes that part of the oxidation-blocking layer on the stepped pattern.

Abstract: In a method of fabricating a semiconductor device, a semiconductor wafer is provided with a plurality of semiconductor elements formed thereon. An insulating adhesive is selectively provided over respective predetermined areas of the semiconductor elements. The semiconductor wafer is then separated into the semiconductor elements, each having corresponding portions of the insulating adhesive thereon.

Abstract: An output driver of a semiconductor integrated circuit having low power consumption and reduced layout area transmits internally generated data of the circuit to pads responsive to clock signals, and is controlled by control signals indicative of changes of process, voltage, and temperature. The output driver includes a data selector, an output driver enabler, a first driver that transmits an output of the output driver enabler to the pads, and a second driver that includes a data delay having a plurality of inverters connected in series to an output of the output driver enabler and being activated responsive to the control signals. The second driver transmits an output of the data delay to the pads. The output driver reduces a load on the clock signal line, so that power consumption and a layout area can be reduced.

Abstract: An operational amplifier includes: a differential input section for generating a first signal corresponding to a differential voltage between two input signals; an amplifying section for amplifying the first signal in voltage to generate second and third complementary signals; a first MOS transistor connected between a first supply voltage and an output node, a conduction state of the first MOS transistor being controlled in accordance with the second signal; a second MOS transistor connected between a second supply voltage and the output node, a conduction state of the second MOS transistor being controlled in accordance with the third signal; and a step-up section for stepping up the first and second supply voltages to generate a step-up voltage higher than the first and second supply voltages; wherein the amplifying section is driven by the step-up voltage so that absolute value of the maximum level of the second or third signal becomes larger than the absolute value of the first or second supply voltage.

Abstract: A method, apparatus and program storage device for analyzing and optimizing equipment efficiency are disclosed. In an illustrative embodiment equipment running time is subdivided into a valuable operating time component and a plurality of performance loss time components. Ideal equipment reference information reflecting dynamic manufacturing parameters is simulated, and an operational performance loss is analyzed in detail. From the analysis of the operational performance loss, priority in input of resources is determined. Advantageously, parameters of a dynamically changing manufacturing environment are incorporated in the analysis and optimization of general equipment efficiency. Moreover, performance loss is more accurately analyzed compared to conventional methods. As such, the performance operating rate is more effectively utilized in reducing performance loss.

Abstract: An inverter circuit includes a first transistor connected between an input terminal and a gate of a second transistor, a second transistor connected between power supply voltage and an output terminal, a third transistor connected between an input terminal and a gate of a fourth transistor and a fourth transistor connected between a ground and the output terminal.

Abstract: A voltage translator enabling a high speed non-selection switching with regard to the word line voltage. The voltage translator (10) includes one inverter (made up of transistors N1 and P1) arranged on the output side of the voltage transistor circuit, a feedback PMOS type transistor (P2), an NMOS type transistor (N4) having a earth terminal and controlled by the output signal from the other inverter newly added on the input side of the voltage translator circuit, an NMOS type transistor (N3) controlled by the word line, and a PMOS type transistor (P3) controlled by a signal given through an NOMS transistor (N2) connected with the output of the above newly added inverter located on the input side of the voltage translator circuit.

Abstract: An E-beam mask for use in a lithographic process includes a main pattern of stripes of patterned chrome or tungsten formed on a membrane. The stripes of the main pattern are inspected for defects. Dummy stripes corresponding to a defective stripe of the main pattern are formed on the membrane in spare room outside the region bounded by the main pattern. E-beam exposure processes are then carried out using only the non-defective stripes of the main pattern, and the non-defective dummy stripes instead of a defective stripe of the main pattern once the lithographic process has progressed to the defective stripe of the main pattern. When the lithographic process is being used to manufacture DRAM cells, some of the stripes of the main pattern will have the same chrome or tungsten patterns. As long as all of these similar stripes of the main pattern are not defective, then the E-beam processes can be carried out in a sequence using the non-defective stripes of the main pattern only.

Abstract: A gate array comprises a core cell having a plurality of logic gates, a power supply pattern provided beside the core cell for providing electrical power to the core cell, and a border element provided beside the power supply pattern for providing capacitance or resistance to the core cell. The border element has a capacity cell including a transistor that provides the capacitance to the core cell, a resistor cell including a transistor that provides resistance to the core cell, and a material having resistance to be provided to the core cell.

Abstract: The invention provides a semiconductor integrated circuit wherein a PMOS 111 having a high threshold voltage is installed between a VDD line 101 and a VDDV line 103, and a NMOS 121 having a high threshold voltage is installed between a VSS line 102 and a VSSV line 104. The semiconductor integrated circuit includes a logic gate circuit supplied with a power source voltage via the VDDV line 103 and the VSSV line 104, respectively, and made up of PMOSes 131 to 133, and NMOSes 141 to 143. A substrate terminal of the PMOSes 131 to 133, respectively, is connected to a pad 163 to which a suitable voltage can be supplied from outside while a substrate terminal of the NMOSes 141 to 143, respectively, is connected to a pad 164 to which a suitable voltage can be supplied from outside. The semiconductor integrated circuit with such a configuration is capable of improving a failure detection ratio at testing.

Abstract: The present invention relates to a liquid crystal display having repair lines and methods of repairing defect in the same. The liquid crystal display comprises a plurality of gate lines in horizontal direction, a plurality of data lines perpendicular thereto, and a plurality of repair lines repeatedly formed corresponding to a fixed number of data lines. The repair line comprises an upper portion crossing top of the data lines, a lower portion crossing bottom of the data lines, and a middle portion which is parallel to the data line connecting the upper and the lower portions. A repair line is formed repeatedly for each data-line block which consists of data lines in any multiples of three. Under the above wiring structure, a disconnected data line is repaired by shorting the crossing points of the data line and the repair line corresponding to the data-line block of the disconnected data line.

Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.

Abstract: A wafer exposure apparatus includes a special wafer cooling unit, namely, an air showerhead, for controlling the temperature of a wafer which is to be transferred from a wafer pre-alignment system to a wafer stage of photolithography exposure equipment. The wafer which has been heated in the course of being transferred from a spin coater to the wafer pre-alignment system, and may be further heated by sensors of the wafer pre-alignment system, is cooled to the same temperature as that of a wafer stage. Accordingly, a thermal equilibrium may be rapidly established between the wafer and the wafer stage when the wafer is transferred to the wafer stage. Accordingly, excessive thermal expansion of the wafer caused by a difference in temperature between the wafer and the wafer stage is prevented. Therefore, an excessive error in aligning the wafer with the optics of the photolithography exposure equipment can be prevented.