Abstract: A wafer is held on the upper side of a chuck. The chuck is connected to a spin motor, a motor-pedestal seat and an air cylinder shaft. The spin motor functions to rotate the chuck while the air cylinder shaft functions to elevate the chuck. When a resist is dropped on the wafer, the air is supplied to the air cylinder concurrently with the rotation of the spin motor, thus causing the chuck to move upward while rotating. The upward movement causes a downward inertial force to act on the resist, which in turn causes the resist to be pressed against the wafer while being dispersed over the surface of the wafer.

Abstract: A method of aligning a wafer for a photolithography process includes establishing a database that includes alignment position data related to the contraction or expansion of a wafer and correcting the data with a compensation value drawn from various specifications of the wafer. The method occurs during a re-alignment of the wafer when measurements indicative of the degree of misalignment of the wafer are outside a prescribed margin for error. The compensation values pertain to the relationship between the step heights of alignment marks formed on the wafers and deposition layers extending over the alignment marks. During the expansion or contraction of the wafer, the deposition layer becomes asymmetrical. The compensation values are a measure of this asymmetry, and hence, are a measure of the discrepancy between the actual position of the alignment mark and the sensed position.

Abstract: In order to solve the aforementioned problems, the present invention provides a semiconductor device having a multilayer interconnection structure, wherein an upper interconnection comprises a first metal layer composed of an aluminum alloy, which is formed over a lower interconnection, and a second metal layer formed over the first metal layer and composed of an aluminum alloy formed as a film at a temperature higher than that for the first metal layer. Another invention provides a semiconductor device having a multilayer interconnection structure, wherein a metal region composed of a metal different from an aluminum alloy is formed in a portion spaced by a predetermined distance in an extending direction of an upper interconnection from an end of a via hole defined in the upper interconnection composed of the aluminum alloy, which is electrically connected to a lower interconnection through the via hole.

Abstract: A refractory metal film is formed over a semiconductor substrate, and a first nitride film is formed over the refractory metal film. Thereafter, the refractory metal film and the nitride film are patterned and the sides of the patterned refractory metal film are nitrided.

Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.

Abstract: An analog storage flash memory by which sufficient write accuracy can be obtained even when the write speed of the memory cell transistor disperses due to manufacturing dispersion or other reasons. A read voltage adjustment circuit outputs the read voltage generated by a read voltage generation circuit as is, or drops and outputs the read voltage. A write voltage adjustment circuit outputs the write voltage generated by a write voltage generation circuit as is, or drops and outputs the write voltage. A write control circuit repeats the write operation at the write voltage Vw until the memory cell transistor turns OFF at the read voltage Vr−&Dgr;Vr in the first write cycle, and repeats the write operation at the write voltage Vw−&Dgr;Vw until the memory transistor turns OFF at the read voltage Vr in the second write cycle.

Abstract: A refrigeration system regulates the temperature of an electrostatic wafer chuck disposed in a process chamber. The refrigeration system includes a heat exchanger disposed in a heat exchange relationship with the electrostatic chuck, a refrigerator, a temperature sensor, and a temperature controller for controlling the refrigerator to cool the coolant withdrawn from the heat exchanger to a desired temperature in response to the temperature detected by the temperature sensor. The heat exchanger forms a coolant passageway inside the electrostatic chuck, and the refrigerator is disposed outside the process chamber. The temperature sensor is disposed within the body of the electrostatic chuck. The temperature of the electrostatic chuck can be regulated so as to be maintained nearly constant because the temperature used to control the cooling of the coolant is measured directly from the body of the electrostatic chuck.

Abstract: A thinner composition is effective in removing a variety of photoresists, and includes propylene glycol mono-methyl ether acetate, ethyl 3-ethoxy propionate and at least one of &ggr;-butyro lactone and propylene glycol mono-methyl ether. The thinner composition can selectively strip a photoresist coated on a backside and at an edge portion of a substrate, as well as a photoresist coated on a whole front surface of the substrate.

Abstract: The polishing particle surface of the dresser of a chemical mechanical polishing apparatus used for a planarization process in manufacturing semiconductor devices is inclined. Moreover, the pressure to be applied onto the polishing surface of the dresser is linearly varied with a nonzero slope.

Abstract: A method for manufacturing a semiconductor memory device includes forming an isolation layer adjacent a diffusion region over a substrate that also has a stacked gate region. A gate oxide layer is formed over the gate region; a first conductive layer over the isolation and gate oxide layers and the diffusion region; a nitride layer over the first conductive layer, the nitride layer having an opening at the isolation layer; and an oxide region in the first conductive layer using the nitride layer as a mask. After removing the nitride layer and the silicon oxide region, an interelectrode dielectric layer is formed over the first conductive layer, and a second conductive layer is formed over the interelectrode dielectric layer. Then, the interelectrode dielectric layer and the first conductive layer over the diffusion portion are removed and a diffusion layer is formed in the substrate of the diffusion portion.

Abstract: A semiconductor device includes an electronic circuit, a metal guard ring surrounding the electronic circuit, and a passivation layer covering the electronic circuit and guard ring. The passivation layer has a slot extending from the surface of the device down to the guard ring. The slot prevents cracks that may form in the passivation layer at the edges of the device from propagating to the area inside the guard ring. Locating the slot over the guard ring enables the size of the device to be reduced, and enables the guard ring to keep moisture and contaminants that enter the slot from reaching lower layers of the device.

Abstract: A digital-to-analog converter which can be used with multi-bit digital codes without increasing the module size thereof, as well as a current source and a differential amplifier, which are preferably used in the digital-to-analog converter. A constant current source supplies a current corresponding to the LSB in a digital code to be converted, resistors generate voltages corresponding to bits other than the LSB in the digital code, and as the generated voltages are applied to the gate terminals of MOSFETs, the MOSFETs permit passage of the currents corresponding to the bits other than the LSB in the digital code. A current source, together with the resistors, provides voltages to be applied to the gate terminals of the MOSFETs, which voltages make the MOSFETs operate in a sub-threshold region, and also make the MOSFETs permit passage of the currents corresponding to the bits.

Abstract: The method for manufacturing a Semiconductor Memory according to the present invention comprises a step for forming a gate insulator film on the surface of a semiconductor substrate; a step for forming a mask layer having a through-hole provided in the position where a tunnel window is to be formed, on top of said gate insulator film; a step for forming an impurity region in the vicinity of the surface of said semiconductor substrate by introducing an impurity using the mask layer; and a step for forming a tunnel insulator film on the surface of the semiconductor substrate, using a mask layer. In the present invention, the position in which the source is formed and the position in which the tunnel window is formed are determined by means of the position of the same through-hole. Therefore, the manufacturing error in the distance between the tunnel window and the source can be nullified.

Abstract: A cassette table on which a wafer cassette is supported allows static electricity to be discharged from the cassette and hence, form the wafers disposed in the cassette. The cassette table includes a top plate, a cassette supporter that is mounted on the top plate and supports the cassette. At least part of the cassette supporter is made of a material that allows static electricity to be discharged to ground therethrough.

Abstract: A phase splitter circuit includes a first signal transfer path for receiving an input signal to output a first output signal, a second signal transfer path for receiving the input signal to output a second output signal having an inverted phase of the first output signal, and a duty cycle correction circuit for controlling pull-up and pull-down speeds of the first and second signal transfer paths to the opposite direction in response to the first and second output signals. According to this structure, duty cycles of the first and second output signals approach 50% and a skew or delay time therebetween approaches “0.

Abstract: A semiconductor device in accordance with the present invention reduces cracks occurring in a junction between a semiconductor device and a mounting substrate due to a heat stress when the semiconductor device is mounted on a printed circuit board or the like. The semiconductor device has a semiconductor element having a thickness of 200 &mgr;m or less, an electrode pad formed on the semiconductor element, a post electrically connected to the electrode pad, and a sealing resin for sealing a surface where circuitry is formed and the post.

Abstract: A polar SAW (Surface Acoustic Wave) filter includes a band-pass ladder type SAW filter having a SAW resonator. A two-terminal pair circuit is serially connected to the band-pass ladder type SAW filter and includes a plurality of inductors. The polar SAW filter has attenuation poles in each of the higher-frequency and lower-frequency attenuation ranges of a pass band.

Abstract: A semiconductor package includes a semiconductor chip having a major surface and first pads formed on the major surface. The semiconductor package also includes a package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces, (c) a pad forming region adjacent to and along the side surface, (d) second pads formed on the pad forming region, (e) external electrodes formed on the first major surface of the package substrate, wherein the second major surface of the package substrate is fixed to the major surface of the semiconductor chip, and wherein the external electrodes are electrically connected to the second pads. The semiconductor package further includes bonding wires electrically connecting the first pads to the second pads and a sealing material covering the bonding wires and first and second pads.

Abstract: A semiconductor integrated circuit device which has a low power consumption in a static state. A first NMOS transistor includes a gate connected to an input, a source connected to ground, and a drain connected to an output. A second NMOS transistor includes a gate connected to the power supply, and a drain and source, one connected to the input terminal and the other to the first NMOS transistor's body. A first PMOS transistor includes a gate connected to the input, a source connected to a power supply, and a drain connected to the output. A second PMOS transistor includes a gate connected to ground, and a drain and source, one connected to the input terminal and the other to the first PMOS transistor's body. Also, the second NMOS transistor's body is connected to ground, or the second PMOS transistor's body is connected to VDD, or both.

Abstract: A semiconductor device includes a semiconductor substrate, a silicon oxide layer formed on the semiconductor substrate, a gate electrode formed over the silicon oxide layer, and a side wall structure formed over the silicon oxide layer and adjacent the gate electrode. In one configuration, the thickness of the silicon oxide layer under the sidewall structure is thicker than the thickness of the silicon oxide layer under the gate electrode.