Abstract: A semiconductor device, which includes a first region having an optical waveguide layer and a second region having a light receiving layer receiving a light from the first region, that improves an intensity of the light from the light receiving layer, and a manufacturing method thereof. An active layer, a cladding layer and a contact layer in a selective growth region of a laser forming region are formed thicker than an absorptive layer, the cladding layer and the contact layer in a modulator forming region A ridge part in the laser forming region therefore has a height greater than that in the modulator forming region, Also in the ridge part, a width of contact surface of the cladding layer with the absorptive layer is greater than a width of contact surface of the cladding layer with the active layer.
Abstract: A semiconductor device fabrication method includes forming a first interconnect and a second interconnect from aluminum or aluminum alloy. The first and second interconnects are formed at different layers and are connected to each other via metal not including aluminum. A hole is provided at the second interconnect, to suppress aluminum loss at ends of the interconnect.
Abstract: A serial access memory low in current consumption, capable of restraining an increase in chip size even if memory capacity increases. The serial access memory has a first and a second memory arrays each having memory cells electrically connected to corresponding bit lines, signal lines provided in common between the memory arrays and electrically connected to the corresponding bit lines through first transfer circuits, write registers electrically connected to the corresponding signal lines through a second transfer circuit, a write bus electrically connected to the write registers through a third transfer circuit, an input circuit electrically connected to the write bus, read registers electrically connected to the corresponding signal lines through a fourth transfer circuit, a read bus electrically connected to the read registers through a fifth transfer circuit, and an input circuit electrically connected to the read bus.
Abstract: There are provided a photosensitive polymer having a copolymer of alkyl vinyl ether and a resist composition containing the same. The photosensitive polymer includes a copolymer of alkyl vinyl ether and maleic anhydride, represented by the following structure:
wherein X is one of a linear alkyl vinyl ether and a cyclic alkyl vinyl ether, which are respectively represented by the structures
wherein y is one of the integer values 1 through 4, R1 is one of a hydrogen atom and a methyl group, R2 is a C1 to C20 hydrocarbon, and R3 is one of a hydrogen atom, a C1 to C3 alkyl group and an alkoxy group.
Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor element on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.
Abstract: A photoresist pattern is formed, without being exposed, by using photoresist having a residual layer proportion characteristic by which the photoresist dissolves at a suitable rate in a developing solution. First, a target layer to be patterned and a photoresist layer are sequentially formed on a substrate having a pattern that defines a step on the substrate. Some of the photoresist layer is treated with the developing solution, to thereby form a photoresist pattern whose upper surface is situated beneath the step and hence, exposes part of the target layer. Next, the exposed part of the target layer, and the photoresist pattern are removed. A silicidation process may be carried out thereafter on the area(s) from which the target layer has been removed. The method is relatively simple because it does not involve an exposure process. Furthermore, the method can be used to manufacture devices having very fine linewidths, i.e.
Abstract: An apparatus and method for forming a HSG silicon layer on a capacitor lower electrode of a semiconductor memory device. The apparatus includes a processing chamber having a plurality of source gas supply nozzles, the lengths of the nozzles being different from one another so as to uniformly supply a source gas. A loadlock chamber is placed under the processing chamber. A boat loaded with wafers is moved from the loadlock chamber to the processing chamber, with the boat being rotated while the source gas is supplied. The processing chamber and loadlock chambers are connected to a vacuum system having two vacuum pumps for maintaining a vacuum in the chambers. A third vacuum pump, connected to the processing chamber, is operated when the vacuum in the processing chamber reaches a predetermined value.
Type:
Grant
Filed:
March 6, 2000
Date of Patent:
January 6, 2004
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Chang-jip Yang, Chan-hee Han, Young-kyou Park, Jae-wook Kim
Abstract: An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.
Type:
Grant
Filed:
November 27, 2002
Date of Patent:
January 6, 2004
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Jong-Myeong Lee, In-Sun Park, Hyeon-Deok Lee, Jong-Sik Chun
Abstract: A cross substrate and a method of mounting a semiconductor element are provided in which semiconductor elements can be mounted at a high density. Element side electrodes of a circuit forming surface of a semiconductor element and conductive filaments of a cross substrate are connected in a one-to-one correspondence by solder bumps. Thereafter, sealing is carried out by using a molten epoxy-based resin. In this way, a circuit forming surface side of the semiconductor element is sealed with sealing resin of the cross substrate, with the element side electrodes of the mounted semiconductor element electrically connected to conductive filaments which are wires of a cross substrate.
Abstract: A signal transmission bus system has a transmission line pair on which binary data values are indicated by the presence and absence of a complementary signal. A driver circuit opens and closes a current path that supplies the complementary signal to the transmission line pair. When this path is opened, the driver circuit closes a bypass current path, so that the driver circuit behaves as a direct-current circuit and does not generate power-supply and ground noise. A receiver that senses the presence and absence of the complementary signal on the transmission line pair includes a differential amplifier and a termination transistor coupled across the input terminals of the differential amplifier, to discharge the input capacitance of the differential amplifier so that high-speed signals can be sensed rapidly.
Type:
Grant
Filed:
January 18, 2001
Date of Patent:
December 30, 2003
Assignees:
Oki Electric Industry Co., Ltd., Sanyo Electric Co., Ltd., Sharp Kabushiki Kaisha, Sony Corporation, Kabushiki Kaisha Toshiba, NEC Corporation, Hitachi, Ltd., Fujitsu Limited, Matsushita Electric Industrial Co. Ltd., Mitsubishi Denki Kabushiki Kaisha, Rohm Co., Ltd.
Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.
Type:
Grant
Filed:
March 4, 2002
Date of Patent:
December 23, 2003
Assignee:
Samsung Electronics Co., Ltd.
Inventors:
Hwa Sung Rhee, Nae In Lee, Jung Il Lee, Sang Su Kim, Bae Geum Jong
Abstract: A semiconductor memory device includes a bit line stack and a storage node contact hole which are aligned at bit line spacers formed at both side walls of the bit line stack and exposes a pad. The semiconductor memory device includes a multi-layered storage node contact plug in which a first storage node contact plug and a second storage node contact plug are sequentially formed. The first storage node contact plug is formed of titanium nitride and the second storage node contact plug is formed of polysilicon. An ohmic layer may be formed on the pad and under the first storage node contact plug. A barrier metal layer, which acts as a third storage node contact plug, may be formed on the second storage node contact plug.
Abstract: An optical wavelength filter having an optical coupler, for suppressing the generation of a double peak caused by a difference of propagation constants between intrinsic modes of light in an optical coupler. The optical wavelength filter includes first and second optical couplers for exciting multiple modes of light in each wavelength of WDM light and providing a phase difference of p/2 between different modes of multiple modes of light, and a mode converter provided between the first and second optical couplers. The mode converter performs mode conversion between the modes of light belonging to a specific wavelength, whereby the phase difference of each mode of light constituting the light of a specific wavelength, and the phase difference between the modes of light constituting the light of another wavelength, are independently adjusted so as to output light of a specific wavelength and light of another wavelength from separate output ports.
Abstract: A power MOSFET is provided. In this power MOSFET, a drift region is formed on a drain region having the same conductivity type as that of the drain region using a semiconductor substrate of a first conductivity type. A gate electrode is formed on the drift region, having a plurality of openings spaced apart from each other by a predetermined distance. The plurality of openings partially expose the drift region, and a gate insulating layer is interposed between the gate electrode and the drift region. A body region of a second conductivity type opposite to the first conductivity type is formed on a predetermined upper region of the drift region and extends from the opening to have a side overlapped by the gate electrode. A channel in the portion of the body region overlapped by the gate electrode is not formed and is adjacent to at least two facing sides of the opening.
Abstract: A management method capable of making an accurate decision about a malfunction of the semiconductor manufacturing equipment includes sampling a plurality of data of at least one parameter under normal operating conditions of the semiconductor manufacturing equipment; generating a Mahalanobis space A from a group of sampled data; calculating a Mahalanobis distance from measured values of the parameter under ordinary operating conditions of the semiconductor manufacturing equipment; and deciding that a malfunction occurred in the semiconductor manufacturing equipment the value of the Mahalanobis distance exceeds a predetermined value.
Abstract: According to an exemplary embodiment of the present invention, an apparatus for selectively introducing birefringence in an optical fiber includes an actuator which selectively exerts a force on the fiber, and a registration key which selectively orients an axis of the optical fiber at predetermined azimuths.
According to another illustrative embodiment of the present invention, an apparatus for changing the polarization state of an optical signal includes a plurality of sequentially connected phase shifters, wherein each of the phase shifters is adapted to exert a force on an optical fiber disposed therein. Each of the plurality of phase shifters includes a registration key which selectively orients an axis of the optical fiber disposed in the registration key at a predetermined azimuth.
Abstract: In a sputtering apparatus for depositing material onto a workpiece, an RF coil is disposed in a chamber between a first target and a workpiece support. The RF coil includes a re-sputtering surface of electrically conductive non-target material which faces towards the workpiece support and which receives a coating of target material for re-sputtering onto the workpiece. A second target, located between the RF coil and the workpiece support, includes a sputtering surface which faces towards the RF coil and which supplies at least a portion of thc coating of target material to the re-sputtering surface of the RF coil.
Type:
Grant
Filed:
January 5, 2000
Date of Patent:
December 9, 2003
Assignee:
Trikon Holdings Limited
Inventors:
Keith Edward Buchanan, Stephen Robert Burgess, Paul Rich
Abstract: A semiconductor package is comprised of a substrate for mounting and fixing a semiconductor element thereon and a connecting pattern. The substrate is provided with a through hall formed therein. The semiconductor element is fixed with its surface where the element is formed being mounted on the substrate and with its electrode being within the through hall. The electrode of the semiconductor element is electrically connected to the connecting pattern via wires through the through hall. The through hall and the wires are sealed with resin.
Abstract: A semiconductor substrate having an upper layer and an alignment mark structure formed on a surface region of the upper layer, the surface region defined by opposite first and second parallel sides extending along the upper layer, outer side walls extending upwardly from the upper layer and extending lengthwise along the side, and are defined lengthwise by alternating first and second wall portions, each of the first wall portions is spaced farther from the first side of the surface region than is each of the second wall portions, and an alignment pattern defined by openings in the alignment mark structure.