Abstract: In accordance with an exemplary embodiment of the present invention, an optical apparatus includes a first optical element, a second optical element, and a third optical element disposed between the first and second optical elements. Light from the first optical element is incident upon the second optical element at an angle with respect to the optic axis that is substantially independent of an offset of the first optical element in a direction orthogonal to the optic axis.

Abstract: In a method for determining the degree of charge-up induced by plasma used for manufacturing a semiconductor device and an apparatus therefor, a predetermined region on a surface of a wafer on which a plasma process has been performed is repeatedly scanned with a primary electron beam. Secondary electrons generated by a reaction between the primary electron beam and the surface of the wafer that are emitted to the outside of the surface of the wafer are collected. The degree of charge-up induced at the surface of the wafer by the plasma used during the plasma process is determined from the change in the amount of collected secondary electrons. Determination as to whether a contact hole is opened or as to the degree of degradation of a gate insulating layer is made based on the degree of charge-up.

Abstract: A method of manufacturing a semiconductor memory element is disclosed. The method includes arranging a mask on the upper surface of a semiconductor substrate, using the mask to conduct exposure, forming first, second, and third element-isolation regions on the semiconductor substrate surface, and forming a gate electrode. A resist film is formed on the substrate. On the mask, auxiliary patterns are made at the each central portion of first, second, and third patterns. In the exposure with the mask, first, second, and third resist patterns is formed on the resist film. The resist patterns respectively correspond to the patterns on the mask. The gate electrode extending in the second direction is formed from the upper surface of the second element-isolation region to the upper surface of the third electrode element-isolation region through an area between the second and third element-isolation regions.

Abstract: A transistor includes a substrate and a gate electrode formed on the substrate and having a wider upper portion than lower portion. A spacer is formed on the side wall of the gate electrode from the upper portion to the lower portion of the gate electrode. A first impurity doped region is formed at an upper portion of the substrate and a second impurity doped region having a higher concentration is formed at a narrower and deeper region than the first impurity doped region.

Abstract: A resist recycling apparatus includes a viscosity control tank supplied with wasted resist liquid; a solvent tank that supplies a solvent to the viscosity control tank; a viscometer that measures viscosity of the resist according to the viscosity measured by the viscometer and the temperature of the resist, and that determines an amount of solvent to supply to the viscosity control tank according to the difference between the calculated resin density and a predetermined resin density; and a filter that removes dust from the resist.

Abstract: In a method for manufacturing a semiconductor device, a semiconductor substrate is provided. On the substrate, conductors spaced apart from one another are formed. Then, an insulating layer is formed on the conductors and the substrate. The insulating layer is formed by a chemical vapor deposition using tetramethylcyclotetrasiloxane as a source gas and oxygen as an adjunction gas. The chemical vapor deposition is performed while the substrate is irradiated by vacuum ultraviolet light. Finally, a part of the insulating layer is removed in a substantial uniform way to form a contact hole through the insulating film.

Abstract: An optical element which controls both the phase and irradiance distribution, thereby completely specifying the E-field, of light, allowing completely arbitrary control of the light at any plane. Such an optical element includes a portion that controls the phase and a portion that controls the irradiance. The portion that controls the irradiance is an apodized irradiance mask having its transmission varying with position in a controlled fashion. This apodized irradiance mask is preferably a pattern of metal. In order to insure a smoothly varying pattern of metal with minimized diffraction effects, a very thin mask spaced from a substrate is used to provide the metal on the substrate. The apodized irradiance mask may be placed directly on the phase control portion, or may be on an opposite side of a substrate of the phase controlled portion.

Abstract: A semiconductor device having a silicon-on-insulator (SOI) structure includes a lower silicon substrate and an upper silicon pattern electrically insulated from the lower silicon pattern by an isolating insulation layer buried by a reverse T-type hole formed in the lower silicon substrate. A gate insulation layer and a gate electrode are formed over the upper silicon pattern, and source/drain regions are formed in the upper silicon pattern centered around the gate electrode. Also, a channel region is disposed between the source/drain region. A silicon layer or a porous silicon layer is formed under the channel region for electrically connecting the lower silicon substrate and the upper silicon pattern. A body contact, which is the same as that of a general semiconductor device, is thus allowed without a special change in the design of the semiconductor device.

Abstract: An nitride semiconductor device for the improvement of lower operational voltage or increased emitting output, comprises an active layer comprising quantum well layer or layers and barrier layer or layers between n-type nitride. semiconductor layers and p-type nitride semiconductor layers, wherein said quantum layer in said active layer comprises InxGa1−xN (0<x<1) having a peak wavelength of 450 to 540 nm and said active layer comprises laminating layers of 9 to 13, in which at most 3 layers from the side of said n-type nitride semiconductor layers are doped with an n-type impurity selected from the group consisting of Si, Ge and Sn in a range of 5×1016 to 2×1018/cm3.

Abstract: A method for erasing data of a nonvolatile memory includes adjusting a threshold voltage of a memory cell transistor to a first threshold voltage; adjusting the threshold voltage of the memory cell transistor to a second threshold voltage, the second threshold voltage being lower than the first threshold voltage; adjusting the threshold voltage of the memory cell transistor to a third threshold voltage, the third threshold voltage being higher than the second threshold voltage and being lower than the first threshold voltage; and adjusting the threshold voltage of the memory cell transistor to a fourth threshold voltage, the fourth threshold voltage being lower than the second threshold voltage.

Abstract: An imaging system and method which successively records parts of a single frame image compensates for variations in intensity of an illuminating source such that the recorded single frame image appears to have been generated by a substantially temporally constant light intensity. This compensation allows inexpensive light sources and detectors to be employed.

Abstract: A semiconductor device includes a low dielectric constant insulating film exhibiting an Si—H Fourier Transform Infrared (FTIR) doublet defined by a first and a second peak, wherein the first peak is located at a higher wave number than the second peak, and wherein the ratio of the first peak to the second peak is greater than unity. A method of producing such a semiconductor device includes depositing a dielectric layer over a substrate and treating the dielectric layer in a hydrogen containing plasma such that the dielectric layer exhibits an Si—H Fourier Transform Infrared (FTIR) doublet defined by a first and a second peak, wherein the first peak is located at a higher wave number than the second peak, and wherein the ratio of the first peak to the second peak is greater than unity.

Abstract: In a photoresist coating apparatus and method, a rotating wafer is scanned with a spray nozzle from which the photoresist issues. The rotational speed of the wafer is varied based on the relative position of the nozzle above the wafer. The varying of the rotational speed is designed to minimize the amount of photoresist necessary for coating the wafer. Specifically, the photoresist is sprayed from the nozzle while the nozzle scans the wafer in a direction from the peripheral edge of the wafer toward its center, and the rotational speed of the wafer is increased during such scanning.

Abstract: This invention relates to a method of etching a substrate in a chamber on an electrostatic chuck, which defines a gas cooling path at the substrate/chuck interface. The method includes electrostatically clamping the substrate on the chuck with gas in the gas path being at a first pressure; etching the substrate at a first power; detecting the end point for the etc; reducing the gas pressure to a second pressure at which the substrate floats on a gas; and over etching the wafer at a second power, which is lower than the first power.

Abstract: A method for inspecting a polishing pad, an apparatus for performing the method, and a polishing device adopting the apparatus for preventing wafer defects. Polishing pad defects are detected by comparing optical data from a normal polishing pad, which does not cause wafer defects, with optical data from a polishing pad to be inspected. The respective optical data are obtained by radiating a beam into the polishing pad and then collecting and analyzing a beam reflected from the polishing pad.

Abstract: An off-leak current cancel circuit includes an input protection circuit having a first protection transistor connected between a terminal and a high power potential, and a second protection transistor connected between the terminal and a low power potential. The first and second protection transistors flow first and second off-leak currents. A current cancel circuit has a first monitor transistor for flowing a third off-leak current that is smaller than the first off-leak current, and a cancellation circuit for flowing the first off-leak current to the low power potential responsive to the third off-leak current. A current providing circuit has a second monitor transistor for flowing a fourth off-leak current that is smaller than the second off-leak current, and a providing circuit for providing the second off-leak current from the high power potential responsive to the fourth off-leak current.

Abstract: There is disclosed an apparatus in the form of a personal computer (1) for conducting a test on a candidate. The computer includes a desktop unit (2) which houses a motherboard, one or more CPU's and any necessary peripheral drivers and/or network cards, none of which are explicitly shown. Computer (1) also includes first means in the form of a screen (3) for presenting a series of questions to the candidate. Also provided are second means in the form of a keyboard (4) for obtaining from the candidate an answer to each of the questions. The CPU included within computer (1) includes timer means which, in this case, is utilised for determining the time taken for the candidate to answer each of the questions.

Abstract: A method for forming isolation regions on a semiconductor substrate, includes partially covering the surface of the semiconductor substrate with oxidation inhabiting films, and heat-treating the portions of the semiconductor substrate which are exposed from the oxidation inhabiting films. The heat treatment consists of a wet-type heating step in a gaseous atmosphere containing oxygen and hydrogen, and a dry-type heating step in a atmosphere without hydrogen which is performed after the wet-type heating step.

Abstract: A semiconductor memory device is fabricated to have a multi-layered structure on a semiconductor substrate. The semiconductor memory device includes ground lines, which are formed in a first conductive layer; bit lines, which are formed in a second conductive layer; and word lines, which are formed in a third conductive layer. The bit lines are not formed in the uppermost conductive layer.

Abstract: A semiconductor device having a trench isolation region including an anti-oxidative liner formed to be thin enough to minimize etch wastage caused by a wet etching solution according to a wet loading effect, and a trench isolation method of forming the same. The semiconductor device includes a silicon substrate and a trench isolation region formed in the silicon substrate. A silicon epitaxial growth layer contacts the silicon substrate at a bottom surface of the trench isolation region and fills the lower half of the trench isolation region. A first oxide layer has an L-shaped cross-section and extends from a sidewall of the trench isolation region to a portion of the bottom surface of the trench isolation region. An anti-oxidative liner has an L-shaped cross-section, and extends between the first oxide layer and the silicon epitaxial growth layer, with its inner surface contacting the silicon epitaxial growth layer.