Abstract: This invention relates to methods and apparatus for delivering liquid precursors to semi-conductor processing apparatus. The liquid precursor delivery system is generally indicated at (10) and includes a source (11), an inlet tube (12), a two-way valve (13), a pump assembly (14), an outlet tube (15), a shut-off valve (16) and a flash evaporator (17). The pump assembly (14) is in the form of a syringe or variable volume pump and is controlled by a combination of a step motor (27) and a linear encoder (30). The arrangement is such that unused liquid precursor can be returned to the source.

Abstract: A redundant memory circuit for use in an analog semiconductor memory has a cell array divided into sectors. To replace bad sectors, the cell array may include a pair of redundant sectors disposed at opposite ends of the cell array, or may have a centrally located redundant sector. Alternatively, the redundant memory circuit may have a sector selection circuit that selects the sectors and redundant sector in sequence from one end of the cell array to the other, or may have a word line selector located in the center of the cell array, or may have two cell arrays and a redundant sector selection circuit that enables a bad sector in one cell array to be replaced by a redundant sector in either of the two cell arrays. These arrangements improve the capability for redundancy replacement and the quality of the reproduced analog signal.

Abstract: A technique of exposing a resist with electron beams having different accelerating voltages is used in a method for manufacturing a photomask. In a first exposing step, an electron beam resist on a substrate is exposed with an electron beam having an accelerating voltage low enough to keep the electron beam resist from developing. In a second exposing step, the electron beam resist is exposed with an electron beam having a higher accelerating voltage. Through the first and second exposing steps, the electron beam resist absorbs an amount of energy greater than the threshold energy, i.e., enough energy to allow the photoresist to be developed. This technique is applied to a resist coating at least one of an opaque layer and a phase shift film form on a transparent substrate. After the resist is developed, the opaque layer and/or phase shift film is etched using the patterned resist as an etching mask.

Abstract: A semiconductor memory device capable of saving power supply voltage and power consumption without increasing the forming area of memory cell array by using MTCMOS technology. In writing data in a memory cell 50-21, a signal RE is turned “H” level, an NMOS 61-1 is turned off and a virtual ground line VGND1 is turned into floating state. When the signal RE is “H” level, the output level of an AND circuit 64-2 turns “L” level and NMOS 55a and 55b turn off. NMOS 53 and 54 turn on by “H” level of a word line WL2 and data in a bit line pair BL1 and BL/ is held on nodes N11 and N12. In reading out data, the signal RE is turned “L” level. When the NMOS 61-1 turns on and the VGND 1 becomes connected to GND, an acceleration circuit 55 accelerates the speed of readout operation.

Abstract: A photosensitive polymer which maintains transparency even when exposed to a short-wavelength light source of 193 nm or below, exhibits improved adhesiveness to a substrate, improved contrast and improved resistance to dry etching. The photosensitive polymer includes a first monomer which is alicyclic hydrocarbon carboxylate having an acid-labile C6 to C20 tertiary alicyclic hydrocarbon group as a substituent, and a second monomer which is capable of free radical polymerization.

Abstract: A memory device employs multiple dual-bank RAMs to allow simultaneous write/read operations. The memory may be utilized in a high-speed block pipelined Reed-Solomon decoder for temporarily storing input codewords during pipelined processing. A memory controller enables writing to and reading from the dual-bank RAMs during each of successive frame periods such that each bank of the dual-bank RAMs is read every given number of frame periods and is written every same given number of frame periods, and such that a read bank is contained in a different one of the dual-bank RAMs than is a write bank in each of the successive frame periods.

Abstract: In a semiconductor memory, memory banks each having memory cells are arranged in X and Y directions. Each of the memory banks include a Y decoder for selecting Y-direction addresses of the memory cells and an X decoder for selecting X-direction addresses of the memory cells, predicated on a memory having memory banks operable independent from one another. Items of data specified by a specified number of continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth (where k=0, 1, 2 . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth in another one of the banks.

Abstract: A level-turning point of input data is detected; and a sampling clock is generated in response to the level-turning point of the input data. The input data are sampled in synchronization with the sampling clock.

Abstract: A first adhesive tape is attached to a first major surface of a semiconductor wafer, the semiconductor wafer having a plurality of semiconductor chip regions. Protrusion electrodes are formed on a second major surface of the semiconductor wafer within the plurality of semiconductor chip regions. Portions of the semiconductor wafer located between the plurality of chip regions are removed to form a plurality of semiconductor chips. Intervals between the semiconductor chips are then expanded. Respective first major surfaces of the wiring substrates are coupled to the corresponding second major surfaces of the semiconductor chips by the protrusion electrodes to form preliminarily structures each of which is comprised of the semiconductor chip and the wiring substrate. A second adhesive tape is attached to second major surfaces of the wiring substrates. The first adhesive tape is removed from the semiconductor chips.

Abstract: A method of fabricating a semiconductor device according to the invention includes forming a capacitor comprising a lower electrode formed on a semiconductor substrate, a capacitive insulator made up of a metal oxide film, formed on the lower electrode, and an upper electrode formed on the capacitive insulator; forming a metal pattern to be electrically connected to the electrodes of the capacitor; forming a first protection film which coats at least a side face of the metal pattern; and forming a water constituents diffusion preventive film on the side face and top face of the metal pattern through the intermediary of the first protection film. As a result, a method of fabricating a ferroelectric memory capable of protecting a ferroelectric capacitor from water constituents evolved during a fabrication process, and maintaining satisfactory memory characteristics can be provided.

Abstract: A package tape for testing a chip assembled by a packaging method such as a micro-ball grid array (BGA) package, whereby the chip is designed to face downward. The package tape includes one or more taps, disposed on a guard area other than an area where a semiconductor chip is attached, for testing the semiconductor chip. One or more pads are disposed on the area where the semiconductor chip is attached and are attached to corresponding test pads on the semiconductor chip. One or more leads which electrically connect the taps with the pads. The package tape advantageously enables easy testing of the electric characteristics of the semiconductor chip, which in a typical BGA package tape cannot be tested by probing since the circuit thereof faces down.

Abstract: In a method for forming a silicon-on-insulator FET having a contact that provides a fixed potential to a substrate, the substrate-biasing between the SOI transistor and the silicon substrate is performed via a plug. As a result, a contact hole for the substrate-biasing does not need to pass through the insulating layer, the silicon layer, and the interlayer insulating layer of the structure. Therefore, the interlayer insulating layer can be made to have shallow depth. Ions can thus be implanted to the surface of the substrate via the contact hole for substrate-biasing. The contact hole for substrate-biasing can be formed without causing an opening fault.

Abstract: A drive circuit for driving a display device includes a voltage level shift circuit which receives a control signal and a data signal and which shifts a voltage level of the control signal and the data signal to output a voltage level shifted control signal and a voltage level shifted data signal. The drive circuit also includes an output circuit which receives the voltage level shifted data signal and which outputs an output data signal corresponding to the voltage level shifted data signal in response to the voltage level shifted control signal.

Abstract: A non-volatile memory includes a substrate: a floating gate electrode and a control gate electrode formed on the substrate; and an active layer formed around the control gate and the floating gate. The active layer has source and drain and a channel layer between the source and drain.

Abstract: A mounting substrate includes a substrate body having at least first and second adjacent chip mounting regions on a surface thereof, and a dicing line between the first and second mounting regions; a first plurality of inner electrodes aligned along a first side of the first chip mounting region; a second plurality of inner electrodes aligned along a second side of the second chip mounting region, wherein the first side of the first chip mounting region confronts the second side of the second chip mounting region; and an interconnect wiring pattern located between the first and second chip mounting regions, and commonly connected to the first plurality of inner electrodes and the second plurality of inner electrodes, wherein the interconnect wiring pattern includes a plurality of connecting wiring portions and at least some of the wiring pattern extends obliquely across the dicing line.

Abstract: An apparatus for grinding wafers includes a grind chuck, formed of a soft material having a high elastic modulus, formed on a grind table. A grind unit grinds the wafer held by the grind chuck. Deionized water is supplied onto the wafer by a supply duct. A dam is formed on the grind table to surround the grind chuck, so that the wafer and the grind unit are submerged during grinding of the wafer. Also, an exhaust hole is formed through the grind table within an area surrounded by the dam, to exhaust the deionized water from the area surrounded by the dam.

Abstract: A variable shaped beam exposure method and a pattern forming method using the same exhibit excellent linearity insofar as the variation in measured critical dimension from design critical dimension is concerned. First, the design critical dimension of one of a plurality of patterns that can be formed through the use of the variable shaped beam exposure method is determined. If the value of the critical dimension exceeds a predetermined value, the selected pattern is formed using a first exposure dose which has previously designated for this case. On the other hand, if the value of the critical dimension is less than the predetermined value, the selected pattern is formed using a second exposure dose that is equal to the first exposure dose plus a supplementary exposure dose.

Abstract: This invention relates semiconductor devices incorporating an intermediate etch stop layer between two dielectric layers in which the dielectric constant of each of the layers is k≦3.5 and the etch stop layer has a selectivity of at least 2.5:1 relative to the upper layer. Methods and apparatus for forming nitrogen doped silicon carbide films, for example, for use as etch stop layers are described.

Abstract: A method of manufacturing an interlayer insulating film that can form an insulating layer having excellent planarization property without using an etch-back process is offered. A method of manufacturing a semiconductor device having a step of forming an interlayer insulating film on an object comprises a step of supplying octa-methylcyclotetrasiloxane as a source gas into a vacuum processing chamber of a vacuum ultraviolet CVD apparatus in which an object on which an interlayer insulating film is to be formed is arranged; and a step of irradiating vacuum ultraviolet light from a vacuum ultraviolet light source arranged on an upper part of the vacuum processing chamber onto the object placed in the vacuum processing chamber to grow an interlayer insulating film.

Abstract: A method for reducing channel skew of a test system which has a plurality of channels and which is used for testing a device connected thereto. The method includes performing system calibration, fine adjusting the test system manually, and recording signal characteristics appearing at the channels during the fine adjusting as eye-shmoo data indicating rising or falling characteristics of signals. Thereafter, system calibration on the test system is performed when a predetermined period has elapsed since the recording, and skew between the channels is then adjusted by performing software processing of the test system using the recorded data. Since the device is not installed in the test system during the test, damage of the test system socket pads may be prevented, so that an error in the test system can be reduced. In addition, time for adjusting channel skew can be reduced.