Abstract: A vibratory conveyor employing an amplitude compensator to substantially impede the conveyor bed from moving beyond a given range of vibration amplitude is described. The amplitude compensator coacts with the conveyor bed as the vibrational amplitude of the bed increases in response to an increase in the mass of conveyed product, or to an increase in the vibrational force produced by the vibratory drive to impede or substantially eliminate premature wear or mechanical failure of leaf springs which support the bed.

Abstract: In one aspect, the invention includes a method of thermal processing comprising: a) providing a semiconductor substrate, the semiconductor substrate supporting a material that is to be thermally processed; b) forming a sacrificial mass over the material, the mass comprising an inner portion and an outer portion, the inner portion having a different composition than the outer portion and being nearer the material than the outer portion; c) exposing the mass to radiation to heat the mass, the exposing being for a period of time sufficient for the material to absorb heat from the mass and be thermally processed thereby; and d) removing the mass from over the material.

Abstract: In one aspect of the invention, an amorphous layer of silicon is provided which has a gradient of thickness variation. The amorphous layer of silicon is transformed into a hemispherical grain polysilicon layer that has varying grain size therein. In another aspect of the invention, a material is provided and has an upper surface and inwardly tapered openings. A first electrically conductive electrode layer is formed within the openings and includes a plurality of hemispherical grain polysilicon layers. At least one of the hemispherical grain polysilicon layers has a grain size gradient defined by a smaller grain size in a region proximate the upper surface and a larger grain size beneath the region with the smaller grain size. An electrically insulative layer is formed over the first electrode layer and a second electrically conductive electrode layer is formed over the electrically insulative layer.

Abstract: A wireless communications system comprising a first transponder adapted to be coupled to one of a plurality of selectable antennas, having a look-up table including locations holding data representing antennas, and having pointers pointing to selected ones of the locations, the pointers defining an order in which antennas will be used to attempt communication; and a second transponder configured to communicate with the first transponder, wherein the first transponder uses an antenna defined by data in one location of the table for communication with the second transponder, and, if successful communication with the second transponder is not established, the first transponder uses an antenna defined by data in another location of the table selected in accordance with the order defamed by the pointers.

Abstract: One aspect of the invention provides a transistor including semiconductive material and a transistor gate having gate oxide positioned therebetween. The gate has opposing gate edges and a central region therebetween, and the gate oxide has opposing edges substantially laterally aligned with the opposing gate edges. A source is formed laterally proximate one of the gate edges and a drain is formed laterally proximate the other of the gate edges. At least one of fluorine or chlorine is concentrated in the gate oxide layer between the semiconductive material and the transistor gate more proximate at least one of the gate edges than the central region. Another aspect of the invention provides a transistor comprising semiconductive material and a transistor gate having gate oxide positioned therebetween. The gate has opposing gate edges and a central region therebetween, and the gate oxide has opposing edges substantially laterally aligned with the opposing gate edges.

Abstract: The invention comprises integrated circuitry fabrication methods of making a conductive electrical connection, methods of forming a capacitor and an electrical connection thereto, methods of forming DRAM circuitry, integrated circuitry, and DRAM integrated circuitry. In one implementation, an integrated circuitry fabrication method of making a conductive electrical connection includes forming a conductive layer including a conductive metal oxide over a substrate. The conductive layer has an outer surface. At least a portion of the conductive layer outer surface is exposed to reducing conditions effective to reduce at least an outermost portion of the metal oxide of the conductive layer, most preferably by removing oxygen. Conductive material is formed over the reduced outermost portion and in electrical connection therewith. In one implementation, integrated circuitry includes a conductive metal oxide comprising layer received over a substrate.

Abstract: An improved manual pump is disclosed. The manual pump comprises a pair of side plates (10), a flexible cylindrical wall (15), a pump chamber (21), an axial shaft (11), a coil spring (12) and a pair of handle bars (16) secured to the side plates (10). When the handle bars (16) are grabbed and clutched with a hand, the side walls (10) are turned in opposite directions, twisting the pump chamber (21) to discharge fluid. The coil spring (12) assists to restore the original shape of the pump chamber (21) to charge fluid.

Abstract: A method of using a phase lock loop to receive an oscillating input signal and produce an output signal, the phase lock loop comprising a plurality of flip-flops which are chained together, the plurality of flip-flops including a first flip-flop having a first output, including a second flip-flop having an input coupled to the first output and having a second output, and including a third flip-flop having an input coupled to the second output, the phase lock loop further comprising a control node, the method including using the flip-flops to determine time spacing between transitions to perform a frequency comparison of the output signal relative to the input signal; extracting a clock from an input digital signal; and performing phase control and adjusting the voltage on the control node of the voltage controlled oscillator.

Abstract: Methods of reducing proximity effects in lithographic processes wherein an integrated circuitry pattern is transferred from a mask onto a semiconductor substrate are described. In one embodiment, a desired spacing is defined between a main feature which is to reside on a mask and which is to be transferred onto the substrate, and an adjacent proximity effects-correcting feature. After the spacing definition, the dimensions of the main feature are adjusted relative to the proximity effects-correcting feature to achieve a desired transferred main feature dimension. In another embodiment, a desired spacing is defined between a main feature having an edge and an adjacent sub-resolution feature. The edge of the main feature is moved relative to the sub-resolution feature to achieve a desired transferred main feature dimension.

Abstract: In one aspect, a deposition method comprises the following steps: a) forming a layer on a semiconductive substrate, the layer comprising predominately an inorganic material, the layer also comprising incorporated carbon; b) generating a plasma adjacent the layer from a component gas, the component gas consisting essentially of N2; and c) utilizing the plasma to remove the carbon from the layer.

Abstract: A method of forming DRAM circuitry includes, a) defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of second conductivity type transistors; b) providing a plurality of patterned gate lines within the array area and the peripheral area, the gate lines defining respective source areas and drain areas adjacent thereto; c) providing capacitor storage nodes over selected array source areas; d) providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the storage nodes and the peripheral area; and e) in two separate photomasking and two separate etching steps, etching the cell plate layer to substantially remove cell plate material from the peripheral area and provide bit line contact openings through the cell plate layer to selected drains in the array area.

Abstract: A method of forming an electrical contact to semiconductive material includes forming an insulative layer over a contact area of semiconductive material. A contact opening is etched through the insulative layer to the semiconductive material contact area. Such etching changes an outer portion of the semiconductive material exposed by the etching. The change is typically in the form of modifying crystalline structure of only an outer portion from that existing prior to the etch. The changed outer portion of the semiconductive material is etched substantially selective relative to semiconductive material therebeneath which is unchanged. The preferred etching chemistry is a tetramethyl ammonium hydroxide solution. A conductive material within the contact opening is formed in electrical connection with the semiconductive material.

Abstract: In one aspect, the invention includes a semiconductor processing method comprising a) forming a metal silicide layer over a substrate; b) depositing a layer comprising silicon, nitrogen and oxygen over the metal silicide layer; and c) while the layer comprising silicon, nitrogen and oxygen is over the metal silicide layer, annealing the metal silicide layer.

Abstract: A semiconductor substrate structure includes a conductor supported by a substrate, and has an outer surface and a pair of spaced-apart conductive sidewalls joining with the outer surface at respective corners. A first layer of material is disposed over the substrate over all of one of the sidewalls, over only a portion of the outer surface and over only a portion of the other sidewall. The first layer of material has a generally uniform thickness over the conductor outer surface, the conductive sidewalls and the corners. A second layer of material having a generally non-uniform thickness is disposed over the substrate. Such has a non-planar outer surface, and an opening therethrough to the conductor's outer surface and the other sidewall which do not have first layer material disposed thereover.

Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.

Abstract: A method of forming integrated circuitry includes forming a field effect transistor gate over a substrate. The gate comprises semiconductive material conductively doped with a conductivity enhancing impurity of a first type and a conductive diffusion barrier layer to diffusion of first or second type conductivity enhancing impurity received thereover. An insulative layer is formed over the gate. An opening is formed into the insulative layer to a conductive portion of the gate. Semiconductive material conductively doped with a conductivity enhancing impurity of a second type is formed within the opening in electrical connection with the conductive portion, with the conductive diffusion barrier layer of the gate being received between the semiconductive material of the gate and the semiconductive material within the opening. Other aspects are disclosed and claimed.

Abstract: In one aspect, the invention encompasses a device for sensing a change in an environment proximate the device. The device includes a planar circuit of conductive material extending along a first plane and comprising at least two sub-circuits which are in parallel electrical configuration relative to one another. The conductive material comprises two ends. The sub-circuits are configured to be broken upon the change in the environment. The device further includes a pair of prongs. A first of the pair of prongs extends from one of the two ends of the conductive material, and a second of the pair of prongs extends from an other of the two ends of the conductive material. The first and second prongs extend along the first plane. Additionally, the device includes a circuit support having circuitry supported thereby and a pair of orifices extending therethrough. The prongs extend through the orifices to electrically connect the circuitry supported by the circuit support to the planar circuit of conductive material.

Abstract: The invention encompasses methods of forming individual silicon-on-insulator layers having varying thicknesses within the individual layers. The invention also encompasses methods of forming transistor devices from silicon-on-insulator layers. Additionally, the invention encompasses semiconductor devices and assemblies utilizing silicon-on-insulator layers. The invention includes a method comprising: a) providing a substrate; b) providing an insulator layer over the substrate; c) providing a semiconductive layer over the insulator layer, the semiconductive layer having a first portion and a second portion; d) forming a depletion region within the semiconductive layer and proximate the insulator layer, the depletion region having a different thickness in the first portion than in the second portion; and f) etching the semiconductive layer to about the depletion region.

Abstract: The invention pertains to semiconductor circuit components and capacitors. In another aspect, the invention includes a capacitor including: a) a first capacitor plate; b) a first tantalum-comprising layer over the first capacitor plate; c) a second tantalum-comprising layer over the first tantalum-comprising layer, the second tantalum-comprising layer having nitrogen; and d) a second capacitor plate over the second tantalum-comprising layer. In another aspect, the invention includes a component having: a) a first tantalum-comprising layer; and b) a second tantalum-comprising layer over the first tantalum-comprising layer, the second tantalum-comprising layer having nitrogen.

Abstract: A method of establishing wireless communications between an interrogator and individual ones of multiple wireless identification devices, the method comprising utilizing a tree search method to attempt to identify individual ones of the multiple wireless identification devices so as to be able to perform communications, without collision, between the interrogator and individual ones of the multiple wireless identification devices, a search tree being defined for the tree search method, the tree having multiple nodes respectively representing subgroups of the multiple wireless identification devices, wherein the interrogator transmits a command at a node, requesting that devices within the subgroup represented by the node respond, wherein the interrogator determines if a collision occurs in response to the command and, if not, repeats the command at the same node.