Patents Represented by Attorney, Agent or Law Firm Wells, St. John, Roberts, Gregory & Matkin, P.S.
  • Patent number: 6258664
    Abstract: In one aspect, the invention includes a method of forming a silicon-comprising material having a roughened outer surface. A semiconductive substrate is provided which comprises conductively doped silicon. A layer comprising silicon and germanium is formed over the substrate. The layer is exposed to conditions which cause crystalline grains within it to increase in size until roughness of a surface of the layer is increased. Dopant is out-diffused from the conductively doped silicon and into the crystalline grains of the layer to conductively dope the layer. In another aspect, the invention includes a method of forming a capacitor construction. A substrate is provided and a conductively doped silicon-comprising material is formed to be supported by the substrate. A layer is formed against the conductively doped silicon-comprising material. The layer has an outermost surface, and comprises silicon and germanium. The layer is subjected to conditions which increase a roughness of the outermost surface.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: July 10, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Alan R. Reinberg
  • Patent number: 6254928
    Abstract: The invention comprises particle forming methods, laser pyrolysis particle forming methods, chemical mechanical polishing slurries, and chemical mechanical polishing processes. In but one preferred implementation, a particle forming method includes feeding a first set of precursors to a first energy application zone. Energy is applied to the first set of precursors in the first energy application zone effective to react and form solid particles from the first set of precursors. Application of any effective energy to the solid particles is ceased and the solid particles and a second set of precursors are fed to a second energy application zone. Energy is applied to the second set of precursors in the second energy application zone effective to react and form solid material about the solid particles from the second set of precursors. Preferably, at least one of the first and second applied energies comprises laser energy.
    Type: Grant
    Filed: September 2, 1999
    Date of Patent: July 3, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Trung Tri Doan
  • Patent number: 6255186
    Abstract: In accordance with one implementation the invention, a capacitor comprises two conductive capacitor electrodes separated by a capacitor dielectric layer, with at least one of the capacitor electrodes comprising at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. In accordance with another. implementation, integrated circuitry includes a conductive silicon containing electrode projecting from a circuit node. A capacitor is received over the silicon containing electrode and comprises a first capacitor electrode having at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. A high K capacitor dielectric layer received over the first capacitor electrode. A second capacitor electrode is received over the high K capacitor dielectric layer.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: July 3, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Husam N. Al-Shareef, Scott Jeffery DeBoer, Randhir P. S. Thakur
  • Patent number: 6255993
    Abstract: An antenna, system and method for transmitting and receiving RF signals over a first frequency band using a single antenna or two closely spaced antennas. In one embodiment, the antenna is configured to receive first signals in the first frequency band having a first rotational polarization and to transmit second signals in the first frequency band and having a second rotational polarization. The second signals may be transmitted in response to the first signals. The first signals may be preferentially routed to a receiver using signal conditioning circuitry that also routes the second signals from a transmitter to the antenna but not to the receiver.
    Type: Grant
    Filed: July 8, 1999
    Date of Patent: July 3, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Roy Greeff, David K. Ovard, Dirgha Khatri
  • Patent number: 6255959
    Abstract: The invention encompasses an electrical apparatus. Such apparatus includes RFID circuitry on a first substrate, and sensor circuitry on a second substrate. A receiving structure is associated with one of the RFID circuitry and the sensor circuitry, and at least one connecting structure is associated with the other of the RFID circuitry and the sensor circuitry. The at least one connecting structure is removable received within the receiving structure. The invention also encompasses a method of forming an electrical apparatus. A first substrate and a second substrate are provided. The first substrate has RFID circuitry thereon, and the second substrate has sensing circuitry thereon. A receptacle is joined with one of the RFID circuitry and the sensor circuitry, and has at least one orifice extending therein. At least one prong is joined with the other of the RFID circuitry and the sensor circuitry.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: July 3, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Rickie C. Lake, Mark E. Tuttle
  • Patent number: 6255213
    Abstract: An electrically conductive apparatus includes, a) an electrically non-conducting substrate, the substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; b) a capping layer of first electrically conductive material coating the elevated surface only portions of the step wall, the capping layer having outer top and outer side portions; and c) a conductive trace of second electrically conductive material which is different from the first electrically conductive material; the conductive trace overlying the substrate, portions of the step wall not covered by the capping layer, and the outer side portions of the capping layer. Methods are disclosed for producing such a construction, for forming an electrically conductive projection outwardly extending from a substrate, and for providing an electrical interconnection between adjacent different elevation areas on a substrate.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: July 3, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Salman Akram
  • Patent number: 6252189
    Abstract: A system and method of operation performing automated optical inspection to remove peel-bearing defective potato pieces from a random mixture of peel-bearing defective and acceptable potato pieces use near infrared light as a source of illumination. The system implements a method of illuminating the mixture with near infrared light, detecting light reflected by the potato pieces under inspection, identifying defective potato piece surface regions based on the detected reflections, and removing the defective items from the mixture. The system and method the system implements permit the inspection of peel-bearing potato pieces for the presence of peel covered and exposed defects.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: June 26, 2001
    Assignee: Key Technology, Inc.
    Inventor: Duncan Campbell
  • Patent number: 6252348
    Abstract: In one aspect, the invention encompasses a field emission display device. The device comprises a base plate and a face plate which is over and spaced from the base plate. The device further comprises emitters associated with the base plate and phosphor associated with the face plate. Additionally, the device comprises a reflector associated with the base plate and having an upper reflective surface. In another aspect, the invention encompasses a method of forming a field emission display device. A base plate is provided, and a pair of spaced emitter-containing regions are provided over the base plate. A reflector is formed over the base plate and between the spaced emitter-containing regions. A face plate is provided, and a pair of spaced phosphor-containing masses are formed in association with the face plate. The face plate and base plate are joined to one another with the face plate being aligned over the base plate and spaced from the base plate.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: June 26, 2001
    Assignee: Micron Technology, Inc.
    Inventor: John Kichul Lee
  • Patent number: 6253298
    Abstract: A synchronous burst SRAM device comprising an SRAM core having a memory array, write drivers, sense amplifiers, and I/O buffers; an address register for receiving addresses for the memory array in the SRAM core; a burst address generator coupled to the address register for rapidly generating additional addresses using at least one address bit stored in the address register; an input for receiving an external address signal indicating that an external address is ready to be loaded into the address register; three chip enable inputs for receiving chip enable signals; chip enable and select logic coupled to the three chip enable inputs to perform the dual tasks of (1) selectively enabling or disabling the synchronous burst SRAM device and (2) selectively permitting access to the SRAM core when the SRAM device is enabled in accordance with a boolean function of the chip enable signals at the three chip enable inputs, the chip enable and select logic outputting an SRAM core enable signal resulting from the boolean
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: June 26, 2001
    Assignee: Micron Technology, Inc.
    Inventor: J. Thomas Pawlowski
  • Patent number: 6251714
    Abstract: A thin film field effect transistor includes: a) a thin film channel region; b) a pair of opposing electrically conductive first and second source/drain regions adjacent the thin film channel region; c) a gate insulator and a gate positioned adjacent the thin film channel region for electrically energizing the channel region to switch on the thin film field effect transistor; d) the first source/drain region having a first thickness, the second source/drain region having a second thickness, the channel region having a third thickness; at least one of the first and second thicknesses being greater than the third thickness. Methods are disclosed for making thin field effect transistors.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: June 26, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Monte Manning
  • Patent number: 6250471
    Abstract: The present invention relates to sorting apparatuses and sorting methods. According to one aspect of the present invention, a sorting apparatus includes an intake section configured to receive plural articles to be sorted; an exhaust section located downstream of the intake section; and an air manifold adjacent the intake section and positioned to emit an air stream in a generally downstream direction and wherein the articles move in a given direction of movement, and the emitted air stream sorts at least some articles from remaining articles and directs the at least some articles in the downstream direction from the intake section to the exhaust section.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: June 26, 2001
    Assignee: Key Technology, Inc.
    Inventors: Robert E. Ruthven, Quentin F. Kemph
  • Patent number: 6251470
    Abstract: In one aspect, the invention encompasses a method of forming an insulating material around a conductive component. A first material is chemical vapor deposited over and around a conductive component. Cavities are formed within the first material. After the cavities are formed, at least some of the first material is transformed into an insulative second material. In another aspect, the invention encompasses a method of forming an insulating material. Polysilicon is deposited proximate a substrate. A porosity of the polysilicon is increased. After the porosity is increased, at least some of the polysilicon is transformed into silicon dioxide.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: June 26, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 6251802
    Abstract: In one aspect, the invention includes an etching process, comprising: a) providing a first material over a substrate, the first material comprising from about 2% to about 20% carbon (by weight); b) providing a second material over the first material; and c) etching the second material at a faster rate than the first material. In another aspect, the invention includes a capacitor forming method, comprising: a) forming a wordline over a substrate; b) defining a node proximate the wordline; c) forming an etch stop layer over the wordline, the etch stop layer comprising carbon; d) forming an insulative layer over the etch stop layer; e) etching through the insulative layer to the etch stop layer to form an opening through the insulative layer; and e) forming a capacitor construction comprising a storage node, dielectric layer and second electrode, at least a portion of the capacitor construction being within the opening.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: June 26, 2001
    Assignee: Micron Technology, Inc.
    Inventors: John T. Moore, Guy T. Blalock, Scott Jeffrey DeBoer
  • Patent number: 6251454
    Abstract: Coated confectionery is formed by introducing pieces of a first confectionery material into recesses in one of a pair of cooled rollers. These are carried around by contra-rotation of the rollers to a nip where chocolate or the like is introduced into the nip to coat the pieces so as to produce the coated confectionery.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: June 26, 2001
    Assignee: Cadbury Schweppes PLC
    Inventor: Edward Layfield
  • Patent number: 6251211
    Abstract: Electrically conductive polymer bumps are formed in electrical connection with circuitry supported by a first substrate. The polymer bumps are bonded with a conductive adhesive to circuitry supported by a second substrate, with the conductive adhesive being in electrical connection with the circuitry supported by the second substrate. Prior to said bonding, an effective amount of ultraviolet radiation is impinged onto the polymer bumps to enhance adhesion of the bumps with the conductive adhesive and electrical conduction between the circuitry of the first substrate and the circuitry of the second substrate. In one implementation, ultraviolet radiation of at least 340 nm is impinged onto conductive polymer bumps prior to subsequent bonding. In one implementation, ultraviolet radiation is impinged onto conductive polymer bumps for a time period less than one minute prior to subsequent bonding.
    Type: Grant
    Filed: July 22, 1998
    Date of Patent: June 26, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Rickie C. Lake
  • Patent number: 6248471
    Abstract: Thin-profile battery electrode connection members, button-type battery electrode connection members, and methods of establishing electrical connections with and between both thin-profile batteries and button-type batteries are described. In one implementation, an electrode connection member comprises an inner conductive surface, and outer peripheral conductive surface, and an intermediate conductive surface joined with and extending between the inner and outer surfaces. The connection member defines an internal volume which is sized to receive at least one thin-profile battery. In one aspect, the intermediate conductive surface tapers between the inner and outer surfaces. The taper enables more than one thin-profile battery to be mounted within the internal volume without the need for edge insulation material over one of the batteries to prevent grounding.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: June 19, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Rickie C. Lake
  • Patent number: 6249191
    Abstract: Monolithic integrated circuit oscillators, complementary metal oxide semiconductor (CMOS) voltage-controlled oscillators, integrated circuit oscillators, oscillator-forming methods, and oscillation methods are described. In one embodiment, a monolithic integrated circuit oscillator is provided and includes a semiconductive substrate. A field effect transistor is supported by the semiconductive substrate and an oscillator circuit is connected therewith. The oscillator circuit preferably comprises an inductor which is supported by the substrate and has an inductance value greater than or equal to about 4 nH. In another embodiment, a complementary metal oxide semiconductor (CMOS) voltage-controlled oscillator is provided and includes a metal oxide semiconductor field effect transistor (MOSFET) received by and supported over a silicon-containing substrate. The transistor has a gate, a source, and a drain.
    Type: Grant
    Filed: November 23, 1998
    Date of Patent: June 19, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 6249185
    Abstract: An amplifier powered by a selectively engageable voltage source and a method for operating the amplifier. The amplifier includes first and second electrodes for receiving an input signal to be amplified. The first and second electrodes are adapted to be respectively connected to coupling capacitors. The amplifier also includes a differential amplifier having inputs respectively connected to the first and second electrodes, and having an output. The amplifier additionally includes selectively engageable resistances coupled between the voltage source and respective inputs of the differential amplifier and defining, with the coupling capacitors, the high pass characteristics of the circuit. The amplifier further includes second selectively engageable resistances coupled between the voltage source and respective inputs of the differential amplifier.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: June 19, 2001
    Assignee: Micron Technology, Inc.
    Inventors: James E. O'Toole, John R. Tuttle, Mark E. Tuttle, Tyler Lowrey, Kevin M. Devereaux, George E. Pax, Brian P. Higgins, David K. Ovard, Shu-Sun Yu, Robert R. Rotzoll
  • Patent number: 6248671
    Abstract: In one aspect, the invention encompasses an apparatus for semiconductor processing comprising: a) at least one support member comprising an upper surface for supporting a semiconductor wafer; b) a component through which the support member extends, the component comprising a front surface and a back surface, at least one of the support member and the component being movable relative to the other of the support member and the component such that the support member can support a wafer in an elevated position above the front surface and can be withdrawn into the component to lower the wafer relative to the front surface of the component; and c) a block joined to the support member below the component back surface, the block engaging the component back surface when the support member upper surface extends above the component to a predetermined distance, the block preventing the support member upper surface from extending beyond the front surface by more than the predetermined distance.
    Type: Grant
    Filed: August 19, 1998
    Date of Patent: June 19, 2001
    Assignee: Micron Technology, Inc.
    Inventors: J. Brett Rolfson, Rodney C. Langley
  • Patent number: D444514
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: July 3, 2001
    Inventors: Donna Joy Jenkins, Vera Signe Lundberg