Abstract: A semiconductor device in which shield wiring is arranged between the semiconductor substrate and the power source wiring for supplying the power source potential or ground potential. Noise, as represented by variations in the potential of the semiconductor substrate, is substantially prevented from transferring to the aforementioned power source wiring by the shield wiring. In one aspect, shield wiring 1 is arranged between Vss wiring for supplying potential to the various circuits on the semiconductor substrate and substrate 7. This shield wiring 1 is connected to grounding lead frame 18 via M1 intra-chip wiring 4, M2 intra-chip wiring 5, connecting part 40, bonding pad 3 and bonding wire 8.

Abstract: A titanium-silicide process using a capping layer to reduce the silicide sheet resistance. A layer of titanium (20) is deposited. A react capping layer (22) may then be deposited to prevent contaminants from entering the titanium layer (20)during the subsequent react step. The layer of titanium (20) is then reacted to form titanium-silicide (32). The react capping layer (22) is then removed and an anneal capping layer (36) is deposited to prevent contaminants from entering the silicide layer (32) during the subsequent anneal step. Then, the silicide anneal is performed to accomplish to transformation to a lower resistivity phase of silicide. An advantage of the invention is providing a silicide process having reduced silicide sheet resistance for narrow polysilicon lines.

Abstract: A unit train (10) includes a base unit (12). Base unit (12) generates a clock signal and a bit signal. Base unit (12) also receives and interprets a data signal. Unit train (10) also includes a plurality of subunits (14) serially coupled in a certain order. Each subunit (14) receives the clock signal and the bit signal. Each subunit (14) also generates a portion of the data signal. Additionally each of the subunits (14) has a corresponding identity. Also included in the unit train (10) is a clock/data line (67) for relaying the clock signal and the data signal between the base unit (12) and each subunit (14).

Abstract: A bipolar transistor (100) and a method for forming the same. A base-link diffusion source layer (118) is formed over a portion of the collector region (102). The base-link diffusion source layer (118) comprises a material that is capable of being used as a dopant source and is capable of being etched selectively with respect to silicon. A barrier layer (119) is formed over the base-link diffusion source layer (118).A base electrode (114) is formed over at least one end portion of the barrier layer (119) and base-link diffusion source layer (118) and the exposed portions of the barrier layer (119) and underlying base-link diffusion source layer (118) are removed. An extrinsic base region (110) is diffused from the base electrode (114) and a base link-up region (112) is diffused from the base-link diffusion source layer (118). Processing may then continue to fore an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: A bipolar transistor (100) and a method for forming the same. A base electrode (114) is separated from the collector region (102) by an insulator layer (110). A doped conductive spacer (115) is formed laterally adjacent the base electrode (114). The conductive spacer (115) comprises a conductive material that is capable of serving as a dopant source for n and p-type dopants and is able to be selectively etched with respect to silicon (e.g., silicon-germanium). Base link-up region (112) is diffused from conductive spacer (115) into the collector region (102). Processing then continues to form an intrinsic base region (108), emitter region (126), and emitter electrode (124).

Abstract: The synchronized transformer-coupled power supply circuit includes a transformer 20; an input power signal coupled to a primary winding 22 of the transformer 20; voltage regulators 48-53 coupled to secondary windings 24 and 26 of the transformer 20; and a start-up circuit 10 for coupling the input power signal directly to one of the voltage regulators 48-51 until the transformer 20 reaches a desired operating level.

Abstract: An improved high-voltage device structure (10, 50, or 60) is a hybrid silicon-based/non-silicon-based power device that has a low R.sub.ds(on) relative to devices formed using only a silicon substrate and includes control circuit (14, 14' or 14") formed on silicon substrate region (12 or 62). High-voltage circuit (16, 16' or 16") is formed in non-silicon substrate region (18). Connecting circuitry (34 and 66) connects control circuit (14, 14', and 14") with high-voltage circuit (16, 16' or 16") to form high-voltage device structure (10, 50 or 60) that has improved control circuit performance and improved high-voltage circuits performance over devices formed solely from a silicon substrate or solely from a non-silicon substrate.

Abstract: A semiconductor integrated circuit for performing a current mirror function and capable of operating stably at a low supply voltage to yield an output current nearly equal to the reference current. The current mirror circuit includes a pair of horizontal type pnp transistors and a vertical type npn transistor having an area almost equal to that of either of the pair of horizontal transistors, the vertical type npn transistor being used as a reverse transistor. A current source supplies the base current of the horizontal transistors as well as the collector current of the vertical transistor. Because of its structure, it is possible for the vertical transistor to have a base area and static forward current transfer ratio greater than those of the horizontal transistors. Since the emitter area of the vertical transistor is large, even when it is used to function as a reverse transistor, its static forward current transfer ratio is high.

Abstract: Disclosed is a magazine for holding semiconductor devices during storage and shipping wherein a portion 22 of the magazine is cut to form a tab 28 which is pushed through an opening 29 in a wall 23 of said magazine to block the end of the magazine, preventing semiconductor devices from falling out of said magazine.

Abstract: For compensating the Early effect a band gap reference voltage source includes current mirror circuits (T.sub.4, Q.sub.3 and T.sub.1, Q.sub.1 as well as T.sub.2, Q.sub.2) to ensure that the currents necessary for achieving the temperature-compensated output voltage are generated. Using the current mirror circuits makes the reference voltage source independent of changes in the supply voltage (U.sub.cc) and enables it in particular to be employed at supply voltages as of low as 3 V.

Abstract: The charge coupled device cell has a semiconductor layer 20 of a first conductivity type, a buried channel 22 of a second conductivity type on the semiconductor layer 20, a first virtual gate 24 in the buried channel 22, the first virtual gate is switched between at least two potential levels, and a first bipolar gate 42 in the buried channel 22 adjacent the first virtual gate 24.

Abstract: A type of semiconductor device with a configuration characterized by the fact that an electroconductive film (90) is formed beforehand in connection to step (54a) of insulating film (54), and an electroconductive layer (63) with step from the aforementioned electroconductive film is coated to form the side contact of the memory cell.Even in the case when breakage takes place in electroconductive layer (63), the electrical conduction is still maintained via substrate electroconductive film (90), and no wire breakage, in effect, takes place. In addition, it is possible to form the pattern for the aforementioned electroconductive layer by, for instance, etching back method without applying a special mask; hence, the manufacturing process is simplified.

Abstract: This invention relates to a method and apparatus for recognizing a script written character. The character is entered using character entering means and digitised by appropriate means. The digitised character is then stored in, for example, a memory. Codes representing topological features of the character are extracted from the character, then the topological features of the character are compared with a set of reference topological features stored in a memory. Each of the set of reference characters corresponding with a specific script written character. A logic process is then performed to determine which of the set of reference features most closely corresponds to the topological features of the digitized character thereby identifying the script written character.

Abstract: A low leakage ESD network (24) is provided for protecting a semiconductor device (22). The ESD network (24) comprises an ESD circuit (28) and a bias circuit (30). The ESD circuit (28) is connected to an input of the semiconductor device (22). The ESD circuit (28) is operable to protect the input of the semiconductor device (22) against electro-static discharge. The bias circuit (30) is connected to the input of the semiconductor device (22) and to the ESD circuit (28). The bias circuit (30) is operable to actively bias the ESD circuit (28) such that a voltage difference across each current leakage path in the ESD circuit (28) is held substantially equal to zero volts during normal operation of the semiconductor device (22).

Abstract: A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.

Abstract: A resin-coated, bonding fine wire for use in forming bonded electrical connections on a semiconductor device, wherein the bonding wire comprises an elongated fine wire of electrically conductive material, and first and second non-conductive coating layers. The first non-conductive coating layer covers the elongated fine wire and is of a material having good insulating property and heat resistance. The second non-conducting coating layer covers the first non-conductive coating layer and is of a material having good abrasion resistance. The first non-conductive coating layer includes at least one aromatic polyester resins, and the second non-conductive coating layer includes at least one resin selected from the group consisting of polyurethanes, polyester imides and polyimides. The second non-conductive coating layer is built up from a plurality of successive coats to define the second non-conductive coating layer as a non-conductive multilayer coating structure.

Abstract: To provide a semiconductor memory device characterized by the fact that it can prevent errors in the redundant memory address coincidence signal generating circuit caused by the intrinsic resistance of the fuse in the fuse decoder, and it has a redundant mechanism for generating the high-speed address coincidence signal. It has multiple logic gate means and fuses programmable by the gate output. The output signal of each fuse is wired to generate address coincidence signal.

Abstract: A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected to receive an input signal (126) on its gate. An MOS state controlling transistor (124) of opposite conductivity type from the MOS logic transistor (122) is connected between the output line (130) and a reference potential (-V.sub.ss), with its gate connected to the gate of the MOS logic transistor (122). A resistor (132) is connected between the supply voltage (128) and the gate of the MOS state controlling transistor (124). If the supply voltage (128) rises above the predetermined level established by the threshold voltage of the MOS state controlling transistor, the MOS state controlling transistor (124) conducts to produce the reference potential on the output line (130).

Abstract: Along the column of bonding pad (1), bonding terminal portions (2c), (3c), (4a), (5a) of bus bars (2), (3), and signal lines (4), (5) are arranged; principal wiring portions (2a), (3a) are made to extend in a 3-dimensional crossing configuration with respect to the signal lines, and they are connected to the bonding terminal portion of the bus bars, forming the IC package of the LOC type. Between the various bonding terminal portions and the various bonding pads, there exists no main wiring portion of the bus bar. Consequently, bonding wires (6), (7), (8), (9) do not straddle the bus bar principal wiring portion. As a result, when the bonding wire is not elevated, the bonding wire still does not make contact with the bus bar principal wiring portion to cause short circuit; as a result, the reliability is high and the device becomes thinner.

Abstract: Microcomputer system providing time management enabling control and acquisition of data indicative of condition changes occurring at high speed. The system comprises a memory plane with associated address decoders and interface circuits which define a switched register zone operably coupled to a memory control logic and a processor via the interface circuits and temporally shiftable therebetween. An address generator is connected to the switched register zone and provides respective addresses thereto in response to an access by the memory control logic. A time base circuit is connected to the switched register zone and to a sequencer which is likewise connected to the switched register zone. An action unit controlled by the time base circuit decodes control commands from the switched register zone. An input unit upon detecting a change of condition (e.g. in an operating engine) generates a capture request signal to the address generator.