Abstract: A system and method for isolating one or more causes of wafer misprocessing. A list of interesting queries (10) is generated. During wafer processing (15), processing parameters are measured (20) and a wafer tracking database (25) is created. The list of queries (10) may be filtered (30) before the queries are tested for interestingness. Interestingness is determined by outlier calculation (35) and trend analysis (40) on data stored in the wafer tracking database (25). Queries found to be interesting are displayed (50).

Abstract: A memory cell system with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

Abstract: Interconnection-pin memory comprising an array of dual-port switching memories used as first-in, first-out devices, characterized in that each dual-port memory (3, 4) of the memory array includes a write-only port (15, 23) and a read-only port (18, 19, 20, 21) having separate address and control signals.

Abstract: An antenna for transmitting rf energy. A polarizer for selectively polarizing the rf energy is operatively connected to a longitudinal shunt slotted plate for radiating rf energy therethrough. A rotational series slotted plate is operatively connected to the longitudinal shunt slotted plate for feeding the rf energy thereto. The plate has slots arranged in columns. First and second dual end slot array feeds are operatively connected to first and second columns of series slots of the rotational series slotted plate, said feeds having first and second input tee junctions. A manifold is operatively connected to the first and second input tee junctions for feeding the rf energy to first and second columns of the slots, the first and second columns of slots having, respectively, n1 and n2 numbers of slots with n1>n2. The manifold includes a power divider, and first and second waveguide lengths connected to the power divider for receiving rf energy.

Abstract: An image array with improved dynamic range has at least one photosite, at least one column sense line and at least one column clamp transistor. A source of the photosite is coupled to the column sense line. A source of the column clamp transistor is coupled to the photosite source. A drain of the column clamp transistor is coupled to a drain of the photosite. A gate of the column clamp transistor is provided for application of a .phi..sub.cc signal. The .phi..sub.cc signal is coupled through a capacitance to the column sense line.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A semiconductor device in which a bit line (41), which is adhered to a contact hole (49) between polysilicon gate electrodes (35) and (36), is directly connected with an SiO.sub.2 film (53) having the same pattern on the gate electrodes; wherein an Si.sub.3 N.sub.4 layer (56) is buried outside the contact areas between the gate electrodes to approximately the same height as the SiO.sub.2 layer (53). The interlayer insulating film of the conventional memory cells array unit is no longer required, and it is not necessary to form contact holes in the interlayer insulating film. As a result, even if the gaps between the gates are designed to be small, there will be no short-circuiting between the bit line and word lines due to mask shifting, etc., making it possible to offer a highly integrated, highly reliable device.

Abstract: A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at a first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.

Abstract: An ESD/EOS protection circuit (100) for protecting an integrated circuit. A MOS transistor (102) is arranged in a multi-finger configuration having a plurality of drain regions (124), a plurality of source regions (122) and a plurality of gates (118). A first metal layer (162) substantially covers each of the drain regions (124) and is in contact with each of the drain regions (124) via drain contacts (130). A second metal layer (154) substantially covers each of the source regions (122) and is in contact with each of the source regions via source contacts (128). A plurality of source contacts (128) are located at a minimum distance from gates (118). Metal-to-metal contacts (160) connect a third metal layer (156) with the second metal layer (154) over each of the source regions (122).

Abstract: A memory cell system is disclosed with properties of asymmetrical operation such that the occurrence of memory error due to certain environmental disturbances is detectable. The asymmetry of operation can be adjusted to set the level at which the disturbance is detected. Detection of memory error in the system can be used to shut off access to an associated memory array in order to prevent error in the array.

Abstract: An isolation structure is disclosed which isolates an active region (24) from other proximate active regions. The isolation structure utilizes the combination of a LOCOS structure (26) comprising bird's beak structure (26a) and (26b). A trench (34) is formed through the LOCOS structure (26). A channel stop implant region (40) is formed along the sidewalls of the trench (34). A trench plug (46) is used to fill the trench. The isolation structure thereby uses the isolation capabilities of trench isolation structures, but prevents the leakage currents common along trench sidewalls by isolating the trench sidewalls from the active region using the LOCOS structures.

Abstract: Voltage regulator control circuit relying upon differential voltage translation and filtering using switched capacitor networks. The voltage regulator control circuit includes a reference input port for receiving an input reference voltage, a controlled-voltage input port for receiving an output voltage from a voltage regulator to be controlled, a capacitor network, a control signal generator, and a switching network for providing controllable connections between capacitors of the capacitor network, the reference input port, the controlled-voltage input port, and the control signal generator. The switching network is operable to alter the controllable connections in a repeating sequence so as to provide an output control signal from the control signal generator which is a measure of the difference between the input reference voltage and the controlled voltage.

Abstract: The process tracking bias generator for antiblooming structures includes a lateral overflow antiblooming drain and bias circuitry coupled to the antiblooming drain for automatically adjusting a bias for the antiblooming drain independent of process variations.

Abstract: A multi-electrode plasma processing system (10) provides flexible plasma processing capabilities for semiconductor device fabrication. The plasma processing equipment (10) includes a gas showerhead assembly (52) a radio-frequency chuck (24), and screen electrode (66). The screen electrode (66) includes base (68) for positioning within process chamber (10) and is made of an insulating material such as a ceramic or teflon. A perforated screen (70) is integral to base (68) and generates a plasma from a plasma-producing gas via a radio-frequency power source (104). The screen (70) has numerous passageways (78) to allow interaction of plasma and the process chamber walls. The screen (70) surrounds showerhead assembly (52) and semiconductor wafer (22) and can influence the entire semiconductor wafer plasma processing environment (62) including the plasma density and uniformity.

Abstract: A method for gray scale printing combining row integration and pulse width modulation. A spatial light modulator (102) has one line (104) designated to perform PWM within a given line time. Another area of the modulator (106) has lines designated to perform row integration on the print image, allowing for more gray levels. An additional area (108) can be designated to correct for defects in the illumination profile and the printed images.

Abstract: Semiconductor processing system for forming a conductive metal film on a semiconductor wafer surface by a sputtering technique, wherein the metal film is to be subsequently patterned into a wiring pattern. The semiconductor processing system includes a support structure for the semiconductor wafer, a fastening device for securing the support structure, and a shielding member which shields the greater part of the area of the support structure and the fastening device for preventing the metal particles being sputtered onto the semiconductor wafer surface from adhering to areas other than the semiconductor wafer surface. The shielding member which may be a shielding plate includes an integral supplementary shielding member in the form of a cylindrical shield defining its system periphery to protect other areas of processing system components from the sputtered metal particles.

Abstract: An anisotropic liquid phase photochemical etch is performed by submersing a substrate 30 (e.g. copper) in a liquid 34 containing an etchant (e.g. hydrochloric acid) and a passivant (e.g. iodine), the passivant forming an insoluble passivation layer 36 (e.g. Cul) on the surface, preventing the etchant from etching the surface. The passivant and its concentration are chosen such that the passivation layer 36 has a solubility which is substantially increased when it is illuminated with radiation 38 (e.g. visible/ultraviolet light). Portions of the surface are then illuminated with radiation 38, whereby the passivation layer 36 is removed from those illuminated portions of the surface, allowing the etch to proceed there. Portions of the surface not illuminated are not etched, resulting in an anisotropic etch. Preferably, an etch mask 32 is used to create the unilluminated areas. This etch mask 32 may be formed on the surface or it may be interposed between the surface and the radiation source.

Abstract: Techniques for achieving high resolution, high-speed gray scale printing with binary spatial light modulators. A spatial light modulator array is divided into subarrays, and the subarrays are illuminated at various levels (510, 512, 514, 516) of a modulated light source. Additionally, each pixel (520) can be divided up into four phases and printed in phase pairs.

Abstract: A plasma processing system 10 for fabricating a semiconductor wafer 24 is disclosed. The system includes a plasma processing tool 12 and an RF energy source 20 coupled to the plasma processing tool 12. An optional matching network 22 may be included between the RF energy source 20 and the plasma processing tool 12. Circuitry 18 for monitoring the RF energy to obtain a measurement characteristic is also provided. At least one transducer 14 or 16 is coupled between the plasma processing tool 12 and the circuitry 18 for monitoring the RF energy. The RF energy is typically applied at a fundamental frequency and the electrical characteristic is monitored at a second frequency different than the fundamental frequency. Also included is circuitry 19, such as a computer, for interpreting the measurement to determine a condition of the processing system 10. Other systems and methods are also disclosed.

Abstract: Integrated circuit with a non-volatile variable resistor which is particularly adapted for use in a neuronic network. The integrated circuit comprises a symmetrically replicated structure including a floating gate MOS transistor (TRP; TRN) and an EEPROM memory cell based upon N-channel MOS transistors and including a read-out MOS transistor (TSP; TSN) and a tunnel-effect charge injection MOS element (TUNP; TUNN), with floating gates. The floating gates of all transistors and of the tunnel-effect element are connected together, with the ends of the resistor (R1P, R2P; R1N, R2N) being taken out from the source and drain regions of the floating gate MOS transistor.