Abstract: An analog/digital converter providing a high conversion speed and resolution while greatly reducing the number of circuit elements. The A/D converter in a first embodiment is a 6-bit resolution flash A/D converter made up of a 3-bit lower A/D conversion section and a 3-bit upper A/D conversion section.

Abstract: A method and apparatus for reducing aperture uncertainty and kick-back noise in high speed comparators is disclosed. The disclosed method is used in a comparator for comparing a first signal (INP) and a second signal (INM) and having a track mode and a regenerative mode of operation. The steps of this method are as follows. A first input current representing the first signal is switched through a first output node (OUTP) during the track mode and a second input current representing the second signal is switched through a second output node (OUTM) during the track mode. During the regenerative mode, approximately half of the first input current is switched through the first output node (OUTP) and approximately half of the first input current is switched through the second output node (OUTM). Also during the regenerative mode, approximately half of the second input current is switched through the first output node and approximately half of the second input current is switched through the second output node.

Abstract: Efficient control of the body voltage embodiment, the body node of a first field effect transistor is connected to the gate of the first transistor through a second field effect transistor. In another embodiment, the body node (p-) of a first transistor is connected to a drain (3) of the first transistor through a second transistor in an area efficient manner. The first and second transistors have a common drain (3) and the gate of the second transistor is an extension of the gate (G) of the first transistor.

Abstract: The invention is to an apparatus and method for applying a plastic material to a lead frame for stabilizing the leads and retaining them in a common plane.

Abstract: A method of implementing pulse-width modulated image display systems (10, 20) with a spatial light modulator (SLM) (15) configured for split-reset addressing. Display frame periods are divided into time slices. Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each pixel element and representing a bit weight of the intensity value to be displayed by that pixel element. Each bit-plane has a display time corresponding to a number of time slices, with bit-planes of higher bit weights being displayed for more time slices. The bit-planes are further formatted into reset groups, each reset group corresponding to a reset group of the SLM (15). The display times for reset groups of more significant bits are segmented so that the data can be displayed in segments rather than for a continuous time. During loading, segments of corresponding bit-planes are temporally aligned from one reset group to the next.

Abstract: A data detection circuit (30) for automatically adjusting to an FSK modulated signal to set a proper trip point for differentiating logic high and low. The detection circuit (30) includes: A demodulator (32) which converts a received FSK modulated signal to voltage levels corresponding to respective frequencies of the modulated signal. A voltage clamp circuit (42) which samples and stores a voltage level of the output of the demodulator (32) and provides a trip point voltage level representing a sum of the stored voltage level and a fixed voltage offset. A comparator (50) which compares the trip point voltage to the voltage levels at the output of the demodulator (32) to provide a logic output signal representing detected digital data signals.

Abstract: A semiconductor processing system (10) is provided that comprises a cleaning chamber (12) and a load lock wafer handler chamber (14). A cleaning agent (34) is placed in a cleaning bath chamber (28). A semiconductor substrate (16) is placed in contact with the cleaning agent (34). Cleaning agent (34) is initially in a liquid phase and is caused to change to a vapor phase so that the cleaning agent (34) can penetrate the topography of the surface to be cleaned. Cleaning agent (34) is then returned to a liquid phase and finally flash-evaporated to complete the cleaning process.

Abstract: A protection circuit (40) providing positive and negative stress protection. A lateral PIN (58) assists in the triggering of a silicon-controlled rectifier (60) for positive stress protection. A vertical PNP (62) provides negative stress protection. A Schottky diode 64 may be used for biasing a n-well (44) to prevent latchup.

Abstract: A switching scheme for driving a three-phase DC motor includes a first end of a first coil 20 coupled to a first end of a second coil 22 and a first end of a third coil 24. A first high side transistor 32 is coupled between a voltage source and a second end of the first coil 20. A second high side transistor 34 is coupled between the voltage source and a second end of the second coil 22. A third high side transistor 36 is coupled between the voltage source and a second end of the third coil 24. A first low side transistor 38 is coupled between the second end of the first coil 20 and a resistor 56. A second low side transistor 40 is coupled between the second end of the second coil 22 and the resistor 56. A third low side transistor 42 is coupled between the second end of the third coil 24 and the resistor 56. An output of a first low side driver 26 is coupled to a gate of the first low side transistor 38. An output of a second low side driver 28 is coupled to a gate of the second low side transistor 40.

Abstract: The charge coupled device charge detection node includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type in the substrate; virtual gate regions of the first conductivity type formed in the second semiconductor layer, the virtual gate regions forming virtual phase potential areas; an insulating layer on the second semiconductor layer; a floating gate formed on the insulating layer, the floating gate is located above a portion of the second semiconductor layer that is between virtual gate regions, the floating gate forming a floating gate potential well in response to a voltage; a first transfer gate formed on the insulating layer and separated from the floating gate by a virtual gate region, the first transfer gate forming a transfer potential area in response to a voltage; and an electrode coupled to one of the virtual gate regions on the opposite side of the floating gate from the first transfer gate, the electrode increases the potential o

Abstract: A logic module for use in gate arrays and the like includes five two input multiplexers 50, 52, 54, 56, 58. The module includes 10 data input terminals I1, I2, I3, I4, I5, I6, I7, I8, I9, I10. The first input terminals I1, I2 are connected to the data input terminals of multiplexer 50. Inputs I3, I4 and I5 are connected respectively to the select, the first data and second data inputs to multiplexer 52. Inputs I6, I7 are connected to the data inputs of multiplexer 54. Inputs I8, I9, I10 are connected to the first data, second data and select inputs to multiplexer 56. The output of multiplexer 52 is connected to the select input to multiplexers 50 and 54. The output of multiplexer 56 is connected to the select input to multiplexer 58 while the outputs of multiplexers 50 and 54 are respectively connected to the first and second data input to multiplexer 58. The output of multiplexer 58 comprises the logic circuit output O.

Abstract: An adder-based base cell (10) is provided for field programmable gate arrays. The base cell (10) includes a first inverter (13) operable to receive a first input signal (A). A first NAND gate (12) is coupled to the first inverter (13) and is operable to receive a second input signal (B). A first 2:1 multiplexer (14) is coupled to the first NAND gate (12) and is operable to receive a third input signal (C). The output of the first 2:1 multiplexer (14) represents a first function (F1). A second inverter (17) is operable to receive a fourth input signal (D). A second NAND gate (16) is coupled to the second inverter (17) and is operable to receive a fifth input signal (E). An XOR gate (18) is coupled to the second NAND gate (16), is operable to receive a sixth input signal (F), and is coupled to the first 2:1 multiplexer (14). The output of the XOR gate represents a partial sum function (PS.sub.-- 1).

Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: The present invention relates to a circuit arrangement integrated in a semiconductor circuit. In modern microprocessor systems with high clock rates (50 MHz and more) special chips with narrow tolerance ranges as regards their switching speed are required. The circuit arrangement according to the invention compensates the switching speed fluctuations due to temperature fluctuations and process spread by generating an internal operating voltage and controlling said voltage in such a manner that it counteracts the fluctuations of the switching speed due to temperature changes and process spread and compensates said fluctuations.

Abstract: An FPGA having a plurality of logic modules with configurable output drivers (8) to enable outputs (y) of several logic modules to be wired together. The output driver (8) comprises a n-channel and a p-channel driver transistor (16, 20) which are connected to a signal (I/O) when no wired outputs (y) are desired. If two or more outputs (y) are to be connected to enable a wired logic function, p-channel transistor (16) is disabled. Then, a weak pull-up transistor (18) may be provided. Alternatively, a senseamp may be provided to the connected outputs (y).

Abstract: A semiconductor memory device with a redundant circuit architecture having improved repairing efficiency and improved yield comprising a memory array (1) divided between a number of subarrays, in which a number of memory cells MCL are arrayed in matrix form; circuits (6-8) and (11-13), which select the subarrays SUB0-SUB7 based on the address signal in order to drive the cell with the specified address; a number of spare word sets SWLS, situated to correspond to the subarrays SUB0-SUB7; a number of fuse sets (3A), which are situated to correspond to the spare word sets SWLS, and which output signals used to replace the selection drive circuit being driven with a spare word set SWLS; and a circuit (3A), used to switch as desired between the output lines for the output signals of the fuse sets; wherein the aforementioned output lines are installed to correspond to the spare word sets (SWLS), and the selection and drive circuits are allowed to select the subarrays SUB0-SUB7 corresponding to the output lines.

Abstract: To provide a type of semiconductor memory device characterized by the fact that the area occupied by the redundant memory address decoder on the chip is minimized without reducing the redundancy of the defective memory, and hence the cost of the semiconductor memory device can be cut.It has both redundant decoders that select the redundant memory in response to the all address bits and the redundant decoders which select the redundant memory group in response to a portion of the address bits, so as to increase the efficiency in saving the defective memory.

Abstract: A MOSFET device (100) having a silicon carbide substrate (102). A channel region (106) of a first conductivity type and an epitaxial layer (104) of a second conductivity type are located above the silicon carbide substrate (102). First and second source/drain regions (118), also of the first conductivity type are located directly within the channel region (106). No well region is placed between the first and second source/drain regions (118) and the channel region (106). A gate (120) is separated from the channel region (106) by an insulator layer (110). Insulator layer (110) has a thin portion (114) and a thick portion (116).

Abstract: A method and apparatus for optimizing a boolean network. The boolean network contains a plurality of functions and a plurality of nodes. Any cube-free divisors (a divisor in which no cube divides the divisor evenly) in the boolean network which apply to at least two of the functions are located (108). The greatest divisor, which is defined as the cube-free divisor which brings about the largest net savings, is determined (114). The net savings comprises both an area savings component and a power savings component. Once the greatest divisor is determined, it is replaced with a variable in each of the functions (116) and added to the boolean network as a new function to create an optimized boolean network (118).

Abstract: Modulator especially for digital cellular telephone systems, characterised in that it comprises a programmable peripheral processor (25) carrying out, with the same circuits, the modulation function and the channel coder/decoder tasks.