Abstract: An input circuit having a CMOS component which outputs correct logical values without through-current flowing when a high level logic output signal V.sub.OH at TTL level is input thereto. The input circuit 1 comprises inverter 20 which outputs by logically inverting the input signals and through-current prevention circuit 21 which stops the flow of current to inverter 20 from power supply V.sub.CC. The through-current prevention circuit 21 comprises reference voltage generating circuit 10, inverters 12 and 13, and MOS transistors 11a, 11b, 14, and 15. The threshold value voltage of inverter 12 is set slightly lower than the high logic level output V.sub.OH at TTL level, and the threshold value voltage of inverter 20 is set lower than inverter 12.

Abstract: A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58).

Abstract: A programmable multizone fluids injector for use in single-wafer semiconductor processing equipment including an injector having a plurality of orifices therein which are divided into a number of separate zones or areas. These zones or areas are connected by means of appropriate passageways and conduits to a source of process fluids. Each of the separate conduits has at least one flow control device located therein for independently controlling the amounts and ratios of process fluids flowing into each zone. The fluid control devices are responsive to input signals so that the fluid flow rates from the orifices can maintain a desired flow pattern within the process chamber to suit the individual needs of a particular fabrication processs.

Abstract: The lateral overflow drain for virtual phase devices includes: a semiconductor region 72 of a first conductivity type; a drain region 24 of the first conductivity type formed in the semiconductor region 72; a threshold adjust region 22 formed in the semiconductor region 72 and surrounding the drain region 24; an electrode 20 overlying and connected to the drain region 24, the electrode 20 overlying and separated from at least a portion of the threshold adjust region 22; and virtual gates 30 and 32 of the second conductivity type in the semiconductor region 72 spaced apart from the drain region 24 and partially surrounding the drain region 24.

Abstract: A method of forming a metal-to-metal antifuse. An antifuse stack 32 is formed comprising a first metal layer 16, an antifuse dielectric layer, and an etchstop layer. The etchstop layer may, for example, comprise an oxide layer 24 and an amorphous silicon layer 28. An antifuse via 44 is etched through an interlevel dielectric layer 36 to the antifuse stack 32. Next, a portion of the etchstop layer at the bottom of via 44 is removed. Finally, a second layer of metal 48 is deposited to fill antifuse via 44 and etched to form the desired interconnections.

Abstract: A regulated cascode circuit with enhanced gain includes a cascode section including a common source MOS transistor (m.sub.1) of a first polarity and a cascode device (m.sub.2) wherein the drain of the common-source MOS transistor (m.sub.1) is coupled to the source of the cascode device. An input to the regulated cascode circuit is applied to the common source MOS transistor (m.sub.1) and an output of the regulated cascode circuit is developed at the drain of the cascode device (m.sub.2) across both the common source MOS transistor (m.sub.1) and cascode (m.sub.2) device. A feedback amplifier circuit (10) has its input (12) connected to the drain of the common source MOS transistor (m.sub.1) and its output (20) connected to a gate of the cascode device (m.sub.2) for driving the cascode device (m.sub.2). The feedback amplifier (10) includes a simple five transistor circuit.

Abstract: An ESD/EOS protection circuit 10. Trigger nMOS transistor M1 has a drain 20 connected to a voltage pad 22, a gate 24 connected to ground 26 and a source 28 connected to ground 26 through source resistor R.sub.e. Switch control nMOS transistor M2 has a drain 30, a gate 34 connected to source 28 of transistor M1, and a source 38 connected to ground 26. Current controlled switch (CCS) 40 is connected to voltage pad 22, ground 26 and drain 30 of transistor M2. CCS 40 is a bipolar pnp-based current controlled switch.

Abstract: A MOSFET device (100) having a silicon carbide substrate (102). A channel region (106) of a first conductivity type and an epitaxial layer (104) of a second conductivity type are located above the silicon carbide substrate (102). First and second source/drain regions (118), also of the first conductivity type are located directly within the channel region (106). No well region is placed between the first and second source/drain regions (118) and the channel region (106). A gate (120) is separated from the channel region (106) by an insulator layer (110). Insulator layer (110) has a thin portion (114) and a thick portion (116).

Abstract: A method of forming a self-aligned silicided gate (44) in a semiconductor device (10). A gate electrode having a conductive body (22) and a disposable cap (24) is formed on the surface of the semiconductor body. A sidewall spacer (32) is formed on the sidewall edges of the gate electrode. A surface dielectric (36) is formed over the exposed semiconductor surface adjacent the sidewall spacers (32) and field insulating layer (18). The disposable cap (24) prevents dielectric formation over gate electrode (22). Source/drain junction regions (34) are formed by ion implantation or another suitable doping method in the surface of the semiconductor body adjacent the gate electrode. The disposable cap (24) is then selectively removed and a silicide layer (40) is formed over the gate electrode using a self-aligned silicide react process. An optional additional self-aligned silicide process may be used to form a source/drain junction silicide layer which is thinner than the gate silicide layer (40).

Abstract: In a method for measuring the consumption of electrical energy by a consumer the momentary values of the alternating voltage and alternating current are measured alternately in the time spacing of a sampling cacle. Each measured momentary value is stored. From the momentary value measured in each sampling period and the stored momentary value the product is formed and the formed products added together. The sum of the products formed is then multiplied by a correction constant depending on the frequency of the alternating current and of the alternating voltage as well as on the sampling period.

Abstract: A high-performance multi-zone illuminator module (130) for directing optical energy onto a semiconductor wafer (60) in a device fabrication reactor to improve overall semiconductor wafer processing uniformity comprises a housing connectable to the wafer processing reactor and having a bottom side and a reflector mounted to the bottom side. The reflector comprises a plurality of concentric circular zones (190, 192, 194 or 270, 262, 266, 264) for reflecting optical energy that include a plurality of circularly distributed lamp sockets (185). Engaged within the lamp sockets (185) are a plurality of point-source lamps (196) for directing optical energy to the semiconductor wafer (60) surface. The point-source lamps (196) are associated with the reflector (184 and 186 or 276 and 277) for directing light toward the wafer. The lamps are associated within each circular zone to provide an approximately continuous and diffused light ring at the semiconductor wafer (60).

Abstract: A tri-state driver circuit is disclosed which provides rail-to-rail output swings and does not consume a significant amount of d.c. power.

Abstract: A multi-zone emissivity correction system and method that may be used in a multi-zone illuminator of a RTP-AVP system. The multi-zone illuminator comprises a plurality of lamps arranged in zones. A dummy lamp is also provided for each zone. A first plurality of sensors monitor the wafer and a second plurality of sensors monitor dummy lamp radiance. For each zone, an emissivity factor is determined based on the first and second pluralities of sensors. An effective black body radiance is also determined for each zone based on a wafer radiance factor for each zone and the emissivity factors.

Abstract: In the modulation and demodulation of a plurality of frequency separated channels on a radio frequency carrier by digitally coded speech or data, the speech or data is modulated on a digitally generated sub-carrier by quadrature phase shift keying and after conversion to analogue form the modulated sub-carrier is mixed with an RF carrier of fixed frequency to produce the signal for transmission. Reception and demodulation of the transmitted signal are effected by the reverse processes. Frequency multiplication is effected after the digital to analogue conversion by producing analogue samples of very short duration and applying them to a suitable filter. Frequency division during the analogue to digital conversion is effected by sub-sampling.

Abstract: A multi-zone lamp interference correction system and method for accurate pyrometry-based multi-point wafer temperature measurement in a multi-zone rapid thermal processing system comprises a plurality of lamps arranged in zones. A dummy lamp is also provided for each zone. Each lamp heating zone and its associated dummy lamp are connected to a controllable power supply. The radiance from a particular zone in the wafer combined with the lamp interference associated with the zone is measured using a first plurality of sensors. The lamp radiation from the plurality of dummy lamps are monitored using a second plurality of sensors. For each zone, a lamp interference component is removed from the wafer temperature sensor signal. The lamp interference components are based on geometry factors and the lamp radiance signals.

Abstract: A contact for a semiconductor device has a via extending through a dielectric and collimated titanium in the via. Depositing titanium by collimation places sufficient metal into high aspect ratio contacts to make good electrical connection. The collimated titanium may be reacted in a nitrogen containing ambient to form a titanium silicide layer at the bottom of the contact and a titanium nitride layer over the titanium silicide layer. The titanium silicide layer provides good electrical contact to a device in a silicon semiconductor substrate and lowers contact resistance. Tungsten may be deposited over the colliminated titanium to form a conductor layer. The titanium nitride layer provides a sticking layer for the tungsten. The contact structure and the method are useful in high aspect ratio contacts present in VLSI multilevel interconnected devices such as dynamic random access memories.

Abstract: The voltage-controlled oscillator (VCO) of the present invention is designed with reduced sensitivity to power supply voltage variations. The VCO includes multiple inverter stages with dc supply inputs tied to a filtered control dc signal, and a disabling circuit for disabling oscillation. The disabling circuit includes a disabling gate connected to the input to said inverter stages and an enabling gate connecting to the output of the inverter stages for enabling transmission of output from the VCO.

Abstract: A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

Abstract: In a semiconductor device having two N type regions separated by a P type region, a channel stop is needed to prevent shorting between the two N type regions. The channel stop of the invention has oxide isolators over the two N type regions and a P+ type diffusion lying between the oxide isolators in the P type region. When the N type regions are phosphorus doped deep N- regions biased at different potentials and the P type region is a boron doped P- region, a shallow P+ boron region within the P- region acts as a blocking mechanism to prevent phosphorus from piling up at the semiconductor surface and shorting the two N- regions. The channel stop may be manufactured without adding additional steps to a CMOS process flow. The oxide isolators may be formed when the oxide isolator over the inverse moat separating the P tank and the N tank is created. The P+ region within the channel maybe formed when the sources and drains for transistors within the N tank are formed.

Abstract: A phase detector circuit (10) for generating an analog signal (VR) dependent upon the phase difference between two digital signals (VE, VA) includes two NOR circuits (20, 27) to the inputs (18, 26; 28, 24) of which the two digital signals are supplied on the one hand delayed and negated and on the other directly. The output signals of the NOR circuits (20, 27) control two current sources (S1, S2), one of which in the activated state furnishes a constant charge current (I1) for a storage capacitor (C) whilst the other of which leads a constant discharge current (I2) of equal magnitude away from said storage capacitor (C). The charge voltage at said storage capacitor (C) is an analog signal (VR) which represents a measure of the phase deviation between the digital signals (VE, VA).