Patents Represented by Attorney William E. Hiller

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  • Synchronous memory with reduced power access mode
    Patent number: 5438548
    Abstract: The synchronous memory (30) includes an address transition detection and control circuitry (42) which detects whether a net change in a selected portion of the address has occurred between consecutive active edges of the clock signal. If an address transition is detected, then a full memory cycle is initiated as usual. However, if no address transition is detected, the amount of activity performed in that memory cycle is reduced or modified to eliminate certain full memory cycle operations. In the reduced power memory cycle, the data already retained by the latches at the sense amplifiers (36) are accessed rather than accessing the memory array (32) for the same data.
    Type: Grant
    Filed: December 10, 1993
    Date of Patent: August 1, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Method for forming a semiconductor on insulator device
    Patent number: 5436173
    Abstract: A method for forming a semiconductor on insulator device is provided that begins with an outer semiconductor layer (16). Trenches (12) of a predetermined depth are formed in outer semiconductor layer (16). An insulator layer (20) is formed outwardly from outer semiconductor layer (16). A mesa (18a) having a predetermined thickness is formed by removing portions of outer semiconductor layer (16) to expose a working surface such that mesa (18a) has a thickness substantially equal to the predetermined depth of the trenches (12) after the working surface is exposed.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Theodore W. Houston
  • Circuit arrangement for monitoring the drain current of a metal oxide semiconductor field effect transistor
    Patent number: 5436581
    Abstract: In the case of a circuit arrangement for monitoring the drain current of a metal oxide semiconductor field effect transistor T.sub.o whose effective transistor area is subdivided in order to provide an MOS measuring transistor T.sub.o ' and an MOS power transistor T.sub.o " the drain-source paths of the two MOS transistor sections T.sub.o', T.sub.o " are placed in different current loops SZ.sub.1, SZ.sub.b of a current mirror SP1, which is acted upon by a predeterminable reference current I.sub.ref. The current mirror SP1 has an output terminal E, which supplies a monitoring signal dependent on the difference between the drain-source voltages of the two MOS field effect transistors T.sub.o', T.sub.o ".
    Type: Grant
    Filed: December 7, 1994
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Deutschland GmbH
    Inventor: Johann Oberhauser
  • Method and apparatus for providing energy to an information handling system
    Patent number: 5436513
    Abstract: An information handling system is described having a power supply (16) having a switching circuit (24) that switches a plurality of energy sources (20) and (22) between series and parallel couplings. Associated with the switching circuit (24) is a voltage level detecting circuit (18) for monitoring the voltage level of the energy sources (20) and (22). A processor (12) for controlling the information handling system (10) responds to the voltage level detecting circuit (18) and in the event of a low voltage condition, the processor (12) activates the switching circuit (24) to switch the energy sources (20) and (22) from a series to a parallel coupling. Alternatively, processor (12) responds to other inputs or conditions for actuating switching circuit (24).
    Type: Grant
    Filed: December 9, 1992
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan A. Kaye, Russell M. Rosenquist
  • CCD image sensor with active transistor pixel
    Patent number: 5436476
    Abstract: An image sensor element having at least one charge storage well 70 and 80, charge transfer structures for transferring charge from one charge storage well 70 to another charge storage well 80, and a charge sensor for sensing charge levels in a charge storage well 70 without removing the charge from the well.Other devices, systems and methods are also disclosed.
    Type: Grant
    Filed: April 14, 1993
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Jaroslav Hynecek
  • Method and apparatus for low-temperature semiconductor processing
    Patent number: 5435379
    Abstract: A chilling system (12) has a container (20) filled with a coolant (22). A pipe (16) traverses within the container (20) and the coolant (22) to a housing (18). Fluid flows within the pipe (16) and becomes chilled through the pipe (16) upon entering the container (20) and the coolant (22). The chilled fluid enters the housing (18) chilling the housing (18) through the pipe (16). In turn, semiconductor substrate (19) in contact with the housing (18) also is chilled.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Mehrdad M. Moslehi, Habib N. Najm, Ajit P. Paranjpe, Cecil J. Davis
  • Methods for adjusting the coupling capacitor of a multi-stage weighted capacitor A/D converter
    Patent number: 5434569
    Abstract: A circuit for adjusting capacitors in a capacitor analog to digital converter has a main capacitor array including more than one capacitor array portion 20 and 22, and at least one first coupling capacitor C.sub.c. A first plate of each first coupling capacitor C.sub.c is coupled to one capacitor array portion 22 and a second plate of each first coupling capacitor C.sub.c is coupled to a next more significant capacitor array portion 20 such that each capacitor array portion is coupled to the next more significant capacitor array portion by one of the first coupling capacitors C.sub.c. The circuit has at least one second coupling capacitor C.sub.c3 with a first plate of each second coupling capacitor C.sub.c3 coupled to the first plate of a corresponding one of the first coupling capacitors C.sub.c.
    Type: Grant
    Filed: September 1, 1993
    Date of Patent: July 18, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Henry T. Yung, Eric G. Soenen
  • Low voltage flash EEPROM memory cell with merge select transistor and non-stacked gate structure
    Patent number: 5432740
    Abstract: A EEPROM memory array (10) includes a plurality of memory cells (24) which are connected in a symmetric array between row lines (26) and Column Lines (28) and Virtual Ground Lines (29). Each of the memory cells includes a merged pass gate which is connected to a control gate. A non-stacked structure is utilized wherein a floating gate (42) is formed, having two portions that extend over an active region, a tunnel diode portion (44) and a control gate portion (46). The floating gate portion (44) is disposed over a thin tunnel oxide layer (47) to form a tunnel diode which allows Fowler-Nordheim tunneling to occur. The control gate portion (46) is disposed over a much thicker oxide layer such that tunneling does not occur. A control gate layer (50) is disposed over the floating gate (42) such that it overlaps the edges thereof and encloses the floating gate (42).
    Type: Grant
    Filed: October 12, 1993
    Date of Patent: July 11, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Iano D'Arrigo, Georges Falessi, Michael C. Smayling
  • Multimode frame transfer image sensor
    Patent number: 5430481
    Abstract: The imager includes a frame transfer image array 22 having a plurality of image cells, the image cells accumulating charge in response to input light and arranged in a plurality of image rows and image columns, odd numbered ones of the image rows constituting a first field and even numbered ones of the image rows constituting a second field; and a memory array 24 having a plurality of memory cells arranged in a plurality of memory rows and memory columns for storing charge from the image array 22, wherein, in a first mode, charge in the first field and the second field is transferred to the memory array 24 from the image array, and, in a second mode, charge in the first field is summed with charge in the second field in the image array 22 before being transferred to the memory array 24.
    Type: Grant
    Filed: March 30, 1994
    Date of Patent: July 4, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Jaroslav Hynecek
  • RF induction plasma source for plasma processing
    Patent number: 5430355
    Abstract: Plasma generator (10) includes chamber (14) for containing the plasma source and a plurality of coils (12) located inside of chamber (14). Located external to chamber (14) are a plurality of permanent multipolar magnets (34) operable to establish a magnetic field in the plasma source along the surface of chamber (14) and a set of electromagnets (36) located outside of chamber (14), which define a preferred propagation direction for a whistler wave in chamber (14). Coils (12) resonantly inductive couple RF power to the whistler wave so as to transfer a sufficient amount of energy to the plasma source to induce a plasma state in the plasma source. Coils (12) also generate time varying electromagnetic fields which also sustain the plasma state in the plasma source.
    Type: Grant
    Filed: July 30, 1993
    Date of Patent: July 4, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Ajit P. Paranjpe
  • Method for constructing semiconductor-on-insulator
    Patent number: 5429955
    Abstract: A method for constructing a semiconductor-on-insulator is provided. A sacrificial layer (12) of a predetermined thickness is first formed on a semiconductor wafer (10) surface. The wafer (10) is then subjected to an ion implantation process to place the ions (16) at predetermined depths below the semiconductor wafer surface. During the implantation process, the sacrificial layer (12) is gradually sputtered away and thereby compensating the gradual outgrowth of the silicon surface due to the volume of the implanted ions (16). A post-implant anneal is performed to allow the ions (16) to react with the semiconductor to form a buried insulating layer (24).
    Type: Grant
    Filed: October 26, 1992
    Date of Patent: July 4, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Keith A. Joyner, Mohamed K. El-Ghor, Harold H. Hosack
  • Apparatus and method for focal plane zoom and pan
    Patent number: 5428390
    Abstract: The apparatus (10) performs pan and zoom functions in conjunction with an electronic image sensor (18) with an image area (72, 92, 112) in which a plurality of lines and columns of pixel data are generated by impinging light. Pan and zoom commands are generated by an input device (12) in response to operator input or commands from a microprocessor and the like. A vertical indexing circuitry (14, 16, 64, 72, 76, 86) is coupled to the image sensor (18) and selectively transfers from the image area (72, 92, 112) a number of successive lines of pixel data in response to the pan and zoom commands. A horizontal indexing circuitry (14, 16, 62, 66, 80, 100, 116) is coupled to the vertical indexing circuitry for receiving the selected number of successive lines of pixel data and further selecting a number of successive columns of pixel data therefrom for display in response to the pan and zoom commands.
    Type: Grant
    Filed: January 21, 1994
    Date of Patent: June 27, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Alan N. Cooper, Jaroslav Hynecek
  • Programmable gate array with special interconnects for adjacent gates and isolation devices used during programming
    Patent number: 5428304
    Abstract: Programmable circuitry (10) is provided including a plurality of logic modules (12) each having at least one input conductor (16). A nearest neighbor conductor (36) is fusibly coupled to output circuitry (25) of a selected logic module (12), the nearest neighbor conductor (36) intersecting the input conductor (16) of a nearest neighbor logic module (12). A fuse (40) disposed at the intersection of the nearest neighbor conductor (36) and the input conductor (16) of the nearest neighbor logic module (12) is provided for selectively establishing electrical coupling therebetween.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: June 27, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Robert J. Landers, Mark G. Harward, Jeffrey A. Niehaus, Daniel D. Edmonson
  • Method for selective removal of hard trench masks
    Patent number: 5425845
    Abstract: After trench formation on a semiconductor wafer (14) using a hard trench mask containing a phosphosilicate glass top layer and an underlying thermal oxide layer, the phosphosilicate glass layer may be removed without substantially etching the thermal oxide layer. The wafer temperature is increased to at least 40.degree. C. (36) prior to etching with an HF/H.sub.2 O vapor (40-44).
    Type: Grant
    Filed: June 9, 1993
    Date of Patent: June 20, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Man Wong
  • Memory cell with programmable antifuse technology
    Patent number: 5426614
    Abstract: A memory cell (10) comprising a first antifuse (A1) operable to place the memory cell (10) in a non-volatile state. In one embodiment, the memory cell (10) comprises a pair of cross-coupled inverters (I1,I2). The first antifuse (A1)is connected between an output (B) of one of the cross-coupled inverters and ground and is operable to place the memory cell in a first non-volatile state. A second antifuse (A2) is connected between an output (B) and a supply voltage (Vcc) and is operable to place the memory cell (10) in a second non-volatile state. Only one of the antifuses, (A1 or A2) is programmed in memory cell (10).
    Type: Grant
    Filed: January 13, 1994
    Date of Patent: June 20, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Mark G. Harward
  • Bulk charge modulated device photocell with lateral charge drain
    Patent number: 5424223
    Abstract: The semiconductor image sensor element comprises a transistor gate potential well 102, a virtual potential well 100 adjacent the transistor gate potential well 102, a clear gate barrier 104 adjacent the virtual potential well 100, a clear drain 30 adjacent the clear gate barrier 104, and a charge sensor 28 for sensing charge levels in the transistor gate potential well 102. The charge levels are responsive to light incident on the device. Charge is stored in the virtual potential well 100 during charge integration. After charge integration, the charge is transferred into the transistor gate potential well 102 from the virtual potential well 100 for charge detection by the charge sensor 28. After charge detection, the charge is transferred from the transistor potential well 102 to the clear drain 30.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: June 13, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Jaroslav Hynecek
  • Method of fabricating precisely matched polysilicon resistors
    Patent number: 5424239
    Abstract: A method of fabricating a resistor which comprises the steps of providing a semiconductor substrate, preferably silicon, forming a layer of oxide over the substrate, providing on the layer of oxide a region of material having a substantially higher resistance in the undoped state than in the doped state, preferably polysilicon, patterning a region over the material to expose predetermined regions of the material, doping the exposed regions of the material to a predetermined doping level substantially greater than the doping level of the original material, masking the doped regions and a portion of the previously unexposed regions of the material on spaced apart portions of the doped regions and etching away the exposed region of material external to the doped regions and external to the portion of the previously unexposed regions of the material on spaced apart portions of the doped regions.
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: June 13, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Frank J. Sweeney
  • Semiconductor memory device and defective memory cell repair circuit
    Patent number: 5422850
    Abstract: To provide a type of semiconductor memory device characterized by the fact that the redundancy for the defective memory of defective bits is increased and the area occupied by the redundant memory address decoder on the chip is minimized, thereby reducing the cost of the semiconductor memory device. It has multiple fuse decoders which are commonly connected to the address bus and are programmed for the different addresses, and it has a redundant address decoder which detects coincidence/uncoincidence between the outputs of the two decoders and generates a redundant address coincidence signal, so as to increase the efficiency in repairing the defective memory.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: June 6, 1995
    Assignees: Texas Instruments Incorporated, Hitachi Ltd.
    Inventors: Shunichi Sukegawa, Tetsuya Saeki
  • Semiconductor memory device having reverse base current bipolar transistor-field effect transistor memory cell
    Patent number: 5422841
    Abstract: A semiconductor memory device, which has a memory cell comprising the following transistors: a transistor for selecting; and a bipolar transistor for memorizing, which has a base region whose base concentration as either lower than an ordinary base concentration or higher than an ordinary base concentration and which is constructed so as to generate a reverse base current.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: June 6, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Osamu Nakayama
  • Technique for enhancing adhesion capability of heat spreaders in molded packages
    Patent number: 5422788
    Abstract: Adhesion between a heat spreader (15) and a substance (19) to be adhered to the heat spreader can be enhanced by using thermal spray deposition to apply a coating (23) to the heat spreader. The substance to be adhered is applied to the coated heat spreader.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: June 6, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Katherine G. Heinen, Brenda C. Gogue, Henry F. Breit