Abstract: Racks of modules especially useful for retaining disk drives, tape drives, controllers, computers and the like are fabricated via use of tower building blocks. Each block contains a latch arrangement for securing it to another block, a base unit or a cap unit with the latch effecting interlocking of the blocks so as to form a sturdy assembled structure. Power and/or electrical communication lines are provided in each block with power passing through one vertical array of blocks and electrical communications passing through the other so as to reduce the need for shielding one from the other. An arrangement of alignment pins and mating receptacle holes in conjunction with selected placement of sliding latch elements can facilitate proper coupling of blocks which have similar electrical path boards therein. Spring elements contained in the latch configuration can include biasing to overcome tolerance build-up and plastic creep from repeated and long term usage.

Abstract: A technique for integrating an internal clock signal with various function commands in an integrated circuit device having an externally supplied clock signal to create a set of command clocks which have the same rising (or falling) edge time, duty cycle and duration and are, therefore, inherently clocked to ameliorate signal “race” and “skew” conditions encountered in prior designs. The technique of the present invention, therefore, improves overall device operational speeds in executing commands by reducing internal gate delays and resulting in faster data access times in integrated circuit memory devices such as synchronous dynamic random access memory (“SDRAM”) devices. Moreover, because the resultant design provides faster operation times, lower cost process technologies may be utilized to achieve substantially comparable performance levels.

Abstract: A memory device including a plurality of sense amplifiers distributed about an integrated circuit chip, where each sense amplifier has a power node for receiving current. A conductor couples the power nodes of a number of sense amplifiers together. A low-impedance power supply conductor extends to each sense amplifier and a local drive transistor is provided for each sense amplifier. A timer unit generates an output signal controlling the local drive transistors. A first component within the timer unit causes the output to change from a first logic level towards a second logic level at a first rate while a second component within the timer unit causes the output to change at a second rate, wherein the second rate is greater than the first rate.

Abstract: Disclosed is a method and apparatus for accessing data in a computer system after a failed data operation in which I/O process state information is unknown. The failed data operation may cause data inconsistency among multiple devices associated with a shadow set for storing data. The disclosed system includes techniques for allowing continued data accesses while simultaneously re-establishing data consistency among members of the shadow set.

Abstract: A yield enhancement technique for integrated circuit processing which reduces the deleterious effects of H2O contamination which is absorbed by conventional dielectric films resulting in an undesired subsequent out-diffusion of hydrogen when the integrated circuit die is subsequently subjected to relatively high processing temperatures such as those experienced in CERDIP packaging. The technique disclosed comprises the formation of an interlevel dielectric layer having hydrophilic properties (for example, 7.5% phosphorus doped TEOS) at least partially surrounding a device on the integrated circuit which layer is then subjected to an annealing operation to drive off at least a portion of any moisture present therein.

Abstract: A system and method for automatically mapping on a computer display a graphical representation of a physical arrangement of a plurality of computer components in one or more cabinets, each cabinet having one or more shelves for housing the computer components. The status of the components is periodically monitored and the computer display updated accordingly. A graphical user interface is provided for user observation of the physical arrangement and status of computer components in the cabinets, as well as user control of the operational parameters of the components.

Abstract: A SCSI bus extender apparatus coupling a main SCSI bus to a auxiliary SCSI bus includes a mechanism for detecting and processing SELECTION and RESELECTION signals transmitted between the two buses to accommodate target devices on the auxiliary bus which support tagged queuing in accordance with the SCSI protocol. The invention contemplates reserving an address on the auxiliary bus for each initiator on the main bus and performing the appropriate address conversions to enable target devices to properly identify the correct initiator device during a RESELECTION phase.

Abstract: A disaster tolerant computer system for protection of electronic databases is achieved by cascading storage controllers to accomplish local and remote disk shadowing. A host computer is connected to a local superordinate storage controller via a local data bus. The superordinate storage controller transmits data via a long haul data link to a remote subordinate storage controller. Additionally, the superordinate controller transmits data to a local subordinate storage controller via a local data bus. Consequently, in-band storage capacity is provided remotely, as well as locally, to increase data storage capacity for database shadowing. Furthermore, the cascading of controllers may be used to increase the effective storage capacity of the computer system by using the increased storage capacity for the writing of non-redundant data.

Abstract: A disk drive processing system controls a Servo Timing Mark (STM) detection window in disk drive during a head switch operation. In response to the head switch operation, the system disables a timer that closes the STM detection window during normal operation, and the system tracks the elapsed time from a time point. The system compares the elapsed time to a programmable limit value. The system resumes normal operation if an STM is detected before the elapsed time reaches the programmable limit value and initiates a recovery procedure if the elapsed time reaches the programmable limit value. Advantageously, the programmable limit value can be easily re-programmed if a larger STM detection window is required due to severe STM or head mis-alignment.

Abstract: An integrated circuit first-in, first-out (“FIFO”) memory device comprises an input bus for receiving data, an input buffer coupled to the input bus for storing the data and at least one dynamic random access memory (“DRAM”) array coupled to the input buffer. A write pointer is operative for storing the data in the input buffer to a location within the memory array indicated and an output bus is coupled to the memory array and a read pointer for providing previously written data from the memory array at a location indicated by the read pointer. In a preferred embodiment, the FIFO further comprises at least one static random access memory (“SRAM”) row, or register, interposed between the input and output buses and the memory array having a width corresponding to each row of the memory array.

Abstract: A method and apparatus for performing head switch operations in a magnetic disk system having a magnetic disk device that is segmented into a plurality of cylinders, which cylinders are grouped into an inner zone, a middle zone, and an outer zone. The inner zone is near the innermost area of the magnetic disk device. The outer zone is near the outermost area of the magnetic disk device. The middle zone is in between the inner zone and the outer zone. The head switch is performed from a current head to a target head. Prior to the head switch, the system determines if the current cylinder is in either the inner zone or the outer zone. When the current cylinder is in either the inner zone or the outer zone, the system seeks the current head to the middle zone, whereupon the system performs a head switch from the current head to the target head. When the current cylinder is not found to be in either the inner zone or the outer zone, i.e.

Abstract: The invention provides a high-speed interface that transfers servo position data from the read channel integrated circuit to the drive control integrated circuit or another integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data which speeds up the data transfer. Examples of servo position data include high-resolution servo position data and coarse-resolution servo position data. A read channel integrated circuit transfers the user data and the high-resolution servo position data to a data bus, such as an NRZ bus. The data bus transfers the user data and the high-resolution servo position data to another integrated circuit, such as a drive control integrated circuit. The other integrated circuit receives the user data and the high-resolution servo position data from the data bus.

Abstract: Metadata described herein on a RAID array includes both device metadata and RAIDset metadata. The device metadata has a device FE bit on each storage device corresponding to each RAID protected block on the storage device. The device FE bit indicates if a corresponding RAID protected block is consistent and thereby useable to regenerate data in another RAID protected block in the corresponding RAID protected block's sliver. The user data also has a forced error bit to indicate if a physical block in the user block has inconsistent data, the RAIDset FE bit. The RAID array of storage devices has user data blocks on each storage device RAID protected by being distributed as slivers of blocks across the RAID array of storage devices. Each sliver has a plurality of user data blocks and one parity block. The RAIDset metadata has the RAIDset FE bit corresponding to each RAID protected user data block in the RAID array.

Abstract: A top surface imaging technique for top pole tip width control in a magnetoresistive ("MR") or giant magnetoresistive ("GMR") read/write head is disclosed in which a multi-layer structure is employed to define the thick photoresist during processing resulting in much improved dimensional control. To this end, a relatively thin upper photoresist layer is patterned with much improved resolution, an intermediate metal or ceramic layer is then defined utilizing the upper photoresist layer as a reactive ion etching ("RIE") mask, with the intermediate layer then being used as an etching mask to define the bottom-most thick photoresist layer in a second RIE process. As a consequence, a much improved sub-micron pole tip width along with a high aspect ratio and vertical profile is provided together with much improved critical dimension control.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory ("DRAM") device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround ("ZBT"), or pipeline burst static random access memory ("SRAM") devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory. Through the provision of a "Wait" pin, the enhanced bus turnaround device of the present invention can signal the system memory controller when additional wait states must be added yet still provide virtually identical data access time performance to that of ZBT SRAM for all Read and Write operations with a burst length of four or greater.

Abstract: A method and apparatus for the establishment of dynamic Enterprise System Connection ("ESCON") connections over a Fibre Channel connection allows a port state machine (or port module) to request dynamic ESCON connections from the exchange context of the Fibre Channel frame and to implement dynamic linking of the Fibre Channel exchanges to ESCON ports while also linking and monitoring the status of these connections for all subsequent frames associated on a particular exchange. In a particular embodiment, the method and apparatus provides the ability to establish dynamic connections through an ESCON Director switch based off of the Originator Exchange Identifier ("OX.sub.-- ID") of the FC-2 header and information contained in the FC-4 header of the Fibre Channel frame. Once a connection path has been established for a particular OX.sub.-- ID, that connection is maintained until the exchange is terminated.

Abstract: A dynamic set/reset circuit is provided with a first feedback line and a second feedback line. The first feedback line provides an interlocked feedback signal which permits high frequency operation of the set/reset circuit. The second feedback line prevents the interlocked feedback signal from causing the circuit to improperly change state until the next cycle of the circuit. In this manner, the circuit will operate properly despite an unexpectedly wide pulse on an input line. The dual feedback can be used on the set or reset inputs of a set/reset circuit, or both, and the set/reset circuit can be used in various logic and high speed applications, such as within a microprocessor.

Abstract: A magnetoresistive read/recording head for use in a fixed disk drive data storage device is formed by the steps of first, photolithographically depositing the head on one surface of a slider block, second, applying, a conductive film preferably of carbon or a silicon/carbon multi-layer film over the head and onto the block surface, and then milling the write tip portion of the head with a focused ion beam. The remaining conductive film is then removed in an oxygen plasma which chemically removes the remaining conductive film. The conductive layer is transparent to the focused ion beam and conducts electrostatic charge away from the head during the milling operation thus preventing electrostatic discharges from occurring which otherwise would damage the head.

Abstract: A switch having a plurality of input/output (I/O) ports and a crossbar device programmably coupling a first of the I/O ports with a second of the I/O ports. A plurality of port request controllers (PRCs) are coupled such that each PRC is associated with one of the I/O ports. A plurality of serial request busses are arranged such that each serial request bus couples each PRC with its associated port. A plurality of serial response busses are coupled such that each serial response bus coupling each PRC with its associated PRC. In operation, the serial request and response busses operate independently in a non-blocking fashion to process connection and clear requests in parallel.

Abstract: Racks of modules especially useful for retaining disk drives, tape drives, controllers, computers and the like are fabricated via use of tower building blocks. Each block contains a latch arrangement for securing it to another block, a base unit or a cap unit with the latch effecting interlocking of the blocks so as to form a sturdy assembled structure. Power and/or electrical communication lines are provided in each block with power passing through one vertical array of blocks and electrical communications passing through the other so as to reduce the need for shielding one from the other. An arrangement of alignment pins and mating receptacle holes in conjunction with selected placement of sliding latch elements can facilitate proper coupling of blocks which have similar electrical path boards therein. Spring elements contained in the latch configuration can include biasing to overcome tolerance build-up and plastic creep from repeated and long term usage.