Abstract: A navigation system for a hierarchy of objects displayed by a computing system are rapidly navigated first by an automatic explosion module for exploding a displayed node of the hierarchy in response to a first characteristic stroke by a pointer control device while the pointer is within the boundary of the displayed node. In addition, an implosion module implodes nodes branching from a displayed node of the hierarchy in response to a second characteristic stroke by the pointer control device while the pointer is within the boundary of the displayed node. The first characteristic stroke by the pointer control device is movement of the pointer controlled by the pointer control device within the boundaries of the displayed node. The second characteristic stroke by the pointer control device is a mouse click while the pointer is within the boundaries of the displayed node or object. A keystroke module sets the level of further explosion of the node when the displayed node is exploded by the explosion module.

Abstract: An apparatus for cutting a substantially cylindrical work piece in a direction generally perpendicular to a longitudinal axis of the work piece includes a wire having a plurality of cutting elements affixed thereto and a wire drive mechanism for driving the wire across and through the work piece. The wire drive mechanism includes a capstan to move the wire orthogonally across a longitudinal axis of the work piece, a rotational drive to oscillate the wire around the longitudinal axis and an advancing drive to advance the wire perpendicularly through the longitudinal axis of the work piece. In a particular embodiment disclosed herein, the apparatus comprises imparts a substantially rocking motion to the wire drive mechanism about the longitudinal axis of the work piece and the cutting elements of the wire are impregnated diamonds.

Abstract: A ferroelectric capacitor includes a bottom electrode, a top electrode, and a ferroelectric layer located between the top and bottom electrodes that extends to completely encapsulate the top electrode, except for a contact hole to allow metalization of the top electrode. The total encapsulation of the top electrode reduces the sensitivity of the ferroelectric capacitor to hydrogen and thus improves electrical switching performance.

Abstract: An apparatus and method for synchronizing a cache mode in a cache memory system in a computer to protect cache operations. The cache memory system has a first controller and a second controller and two cache modules and operates in a plurality of cache modes. The cache mode is stored as metadata in the cache modules and is detected by the first controller to determine the cache mode. Lock signals in the first controller are set in accordance with the cache mode detected to set the cache mode state in the first controller. The second controller copies the cache mode state from the first controller to synchronize both controllers in the same cache mode state. After a failure of the second controller, the first controller may lock access to both caches to recover data previously accessed by the second controller. The second controller restarts and copies the cache mode state from the first controller, so that both controllers return to the cache mode state prior to the failure of the second controller.

Abstract: The present invention involves a charge pump including an input node coupled to receive an input voltage from a power voltage source and an oscillator unit generates a periodic enable regulator signal and a periodic reset signal. A regulator clock unit is coupled to the oscillator unit generating a precharge (PC) signal and a reset regulator signal in response to the enable regulator signal. A pump clock unit receives a master clock signal and generating a plurality of pump clock signals. A charge pump unit is coupled to the input node and is operatively controlled by the plurality of pump clock signals, and coupled to the an output terminal coupled to produce an output signal (VPUMP). A regulator unit is coupled to receive the VPUMP signal, the PC signal, the reference signal and the enable regulator signal, where the regulator unit is responsive to the enable regulator signal to operate in either a precharge mode or a regulation mode.

Abstract: In a storage system having a plurality of disks arranged in a RAID array with one of the disks failed, a method of reorganizing the data on the RAID array at the time of failure to prevent both a decrease in performance of the array and reliability of the data and an increase in the cost of operation. Data from the failed disk is regenerated one strip at a time and written onto the original parity chunk for the strip. The resulting fully folded array has the characteristics of a RAID level 0 array. When a replacement disk is inserted into the array the process is reversed to bring the fully folded array back to a fully redundant condition.

Abstract: An integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache integrated monolithically therewith improves the overall access time in page and provides faster cycle time for read operations. In a particular embodiment, the cache may be provided as static random access memory (“SRAM”) and the non-volatile memory array provided as ferroelectric random access memory wherein on a read, the row is cached and the write back cycle is started allowing subsequent in page reads to occur very quickly. If in page accesses are sufficient the memory array precharge may be hidden and writes can occur utilizing write back or write through caching.

Abstract: A system for preventing crosstalk noise in a head of a drive for a reading data from and writing data to a magnetic media. The present invention includes circuitry that applies an intermediate current to a write element after a write operation is complete. The intermediate current causes the magnetic domains of the write element to go from a high energy state to an intermediate energy state before going to a low energy state. This reduces the magnetic pulses emitted from the write element.

Abstract: In a data storage system a number of records are prefetched from large volume storage devices for transfer to a cache in order to return requested records to a host computer in response to a read request from the host computer. If a previous prefetch is not complete when the read request is received, the number of records in a next prefetch of records is increased by a preset amount. If a previous prefetch is complete, a next prefetch of records is initiated with the same number of records in the prefetch as the previous prefetch. The initiation of prefetch operations is triggered by detection of a sequential read stream in a plurality of read requests from the host computer. When the prefetch size is increased, the preset amount of the increase equals the number of records in the read request from the host computer. After requested records are returned from the cache to the host computer in response to the read request, storage space in the cache used by the returned requested records is released.

Abstract: A hydrogen barrier encapsulation technique for the control of hydrogen induced degradation of ferroelectric capacitors in non-volatile integrated circuit memory devices. The resultant device structure ameliorates the hydrogen induced degradation of ferroelectric capacitors by completely encapsulating the capacitor within a suitable hydrogen barrier material, such as chemical vapor deposition (“CVD”) or sputtered silicon nitride, thus ensuring process compatibility with industry standard process steps. Although the deposition process for CVD Si3N4 itself contains hydrogen, the deposition time may be kept relatively short thereby allowing the TiN local interconnect layer to act as a “short term” hydrogen barrier.

Abstract: An integrated circuit memory device and method incorporating Flash and ferroelectric random access memory arrays integrated on a common substrate. The present invention allows a relatively small amount of ferroelectric random access memory to mitigate many of the erase and write time disadvantages exhibited by current Flash technology devices. In particular, whether combined together as a single stand-alone memory device or embedded together as a portion of a processor, microcontroller or application specific integrated circuit (“ASIC”), a block of ferroelectric memory that is sized to match the largest sector of Flash memory can effectively compensate for the latter's slow erasure and write times.

Abstract: A method and mechanism for controlling network bandwidth by dynamically determing a current window size for a destination buffer. A first window size is determined for the destination buffer at a first time. Then, a current window size is determined a second time as a function of the first window size, a desired bandwidth value, and a bandwidth used between the first time and the second time. A desired bandwidth for a particular connection is achieved by an adaptive or delta-based approach rather than by use of round trip time (RTT) computations. Bandwidth control can be achieved by a software or a hardware bandwidth control mechanism. Possible applications of the bandwidth control is in a server or a quality of service unit.

Abstract: A server extension architecture provides means for intercepting input events and output protocol requests. Remote terminal emulation on an XWindows system is possible. The architecture comprises a portion of memory in the server extension which is identical to a portion in memory in the server where the server stores the addresses of input and output handling routines. By swapping these addresses with addresses in the server extension portion of memory, the server extension intercepts input and output, for monitoring a server or an application program or controlling a workstation. The server extension architecture is operated under the control of an application program.

Abstract: A network element maintains a local representation of a variable from a network directory service without needing to poll the variable in the directory service. The network element is arranged to accept replication messages from the directory service for updating the local record. By using a replication mechanism, it is possible to maintain the current value of a variable without repeated polling of the variable in the directory service.

Abstract: A multiprocessor computer architecture incorporating a plurality of programmable hardware memory algorithm processors (“MAP”) in the memory subsystem. The MAP may comprise one or more field programmable gate arrays (“FPGAs”) which function to perform identified algorithms in conjunction with, and tightly coupled to, a microprocessor and each MAP is globally accessible by all of the system processors for the purpose of executing user definable algorithms. A circuit within the MAP signals when the last operand has completed its flow thereby allowing a given process to be interrupted and thereafter restarted. Through the use of read only memory (“ROM”) located adjacent the FPGA, a user program may use a single command to select one of several possible pre-loaded algorithms thereby decreasing system reconfiguration time.

Abstract: The present invention is a fiber channel switch employing a distributed queuing algorithm for interconnecting a plurality of devices (workstations, supercomputer, peripherals) through their associated node ports (N_ports) and employs a fabric having a shared memory coupled to a plurality of fabric ports (F_ports) through a bi-directional bus over which memory addresses, frame data and communications commands are transmitted. Each F_port includes a port controller employing a distributed queuing algorithm associated with a control network for communicating commands between the ports related to when and where frame transfers should be made, wherein the bi-directional bus provides an independent data network for access to the shared memory such that frames can be transferred to and from the shared memory in response to port controller commands.

Abstract: A switch including a plurality of input/output (I/O) ports and a switching element programmably coupling a first of the I/O ports with a second of the I/O ports. An analysis device is associated with the first I/O port measuring at least one data traffic parameter specific to data traffic between the first I/O port and the second I/O port.

Abstract: A system and method exclusively accesses a shared storage location using a shared algorithm. Competing processors follow the algorithm for reserving exclusive access to the shared storage location. Those competing processors that have not successfully reserved exclusive access honor the reservation of the successful processor and delay their own access attempts. Two critical storage blocks and two delay times are typically used during an attempt to reserve exclusive access for a processor.

Abstract: A highly precise range measurement instrument is made possible through the use of a novel and efficient precision timing circuit which makes use of the instrument's internal central processing unit crystal oscillator. A multi-point calibration function includes the determination of a “zero” value and a “cal” value through the addition of a known calibrated pulse width thereby providing the origin and scale for determining distance with the constant linear discharge of capacitor.

Abstract: An apparatus and method for measuring coefficients of retroreflectance of retroreflective surfaces such as road signs involves use of a modified light based range finder. The apparatus includes a power attenuation factor data base which relates pulse width of received pulses to power attenuation of the transmitted pulses. The range finder calculates target range based on time of flight of light pulses. The apparatus automatically calculates the absolute coefficient of retroreflectance for an unknown reflective surface being measured by comparison of the measurement to a reading with the same instrument of a known reflectance standard.