Abstract: An integrated circuit memory device including at least one memory bank with the memory bank being logically partitioned into even and odd portions thereof. Even and odd data buses are provided which are selectively couplable to the even and odd portions of the memory banks respectively for placing read data thereon by means of corresponding first multiplexers in response to a first control signal. A read pipeline sorting block is coupled to the even and odd data buses for selectively applying the read data on the even data bus to either of a rising or falling edge data output bus and the read data on the odd data bus to an opposite one of the rising or falling edge data output buses.

Abstract: A technique for forming a borderless transistor gate and source/drain region contact structure which provides an on-chip area efficient layout and connection between the device gate layer and an associated source/drain region that can also overlap adjoining isolation structures. In a representative embodiment, this may be effectuated through the overlapping of one portion of the contact region over the edge of the gate polysilicon layer and another part of the contact over the source/drain diffusion. The structure and process of the present invention provides a desirable size reduction in the contact for given design rule dimensions and the resultant contact structure is inherently “self-aligned” to both the gate polysilicon layer and the isolation region in that the contact has no need for an interstitial space between it and the gate polysilicon or isolation regions to prevent unintended electrical connections.

Abstract: A double data rate (“DDR”) synchronous dynamic random access memory (“SDRAM”) device incorporating a static random access memory (“SRAM”) cache per memory bank that provides effectively double peak data bandwidth, optimizes sustained bandwidth and improves bus efficiency as compared with conventional DDR SDRAM devices. The memory device disclosed provides effectively faster basic DRAM memory latency parameters, faster page “hit” latency, faster page “miss” latency and sustained bandwidth on random burst reads, faster read-to-write latency and write-to-read latency, hidden precharge, hidden bank activate latency, hidden refresh and hidden write precharge during a read “hit”.

Abstract: A cache system and method for configuring and accessing a cache that enables a binary-sized memory space to be efficiently shared amongst cache and non-cache uses. A storage device is provided having a plurality of blocks where each block is identified with a block address. An access request identifies a target block address. The target block address includes an upper portion and a lower portion. A non-binary divide is performed on the upper portion to produce a quotient and a remainder. The remainder portion is combined with the lower portion to create an index. The index is applied to a tag memory structure to select an entry or set of entries in the tag memory structure. The content of the selected entry is compared to the quotient portion to determine if the target block is represented in the cache.

Abstract: The invention provides a high-speed interface that transfers user data and other data over a single unified interface between a read channel integrated circuit and another integrated circuit, such as the drive control integrated circuit. The high-speed interface eliminates the need for analog pins on the integrated circuits to lower the cost of the system. The high-speed interface also eliminates the use of the serial interface to transfer the servo position data and other data which speeds up the data transfer. Examples of the other data include read channel settings, read channel performance data, and servo data. A read channel integrated circuit exchanges the user data with a data bus when the disk drive system is reading or writing the user data. The read channel integrated circuit exchanges the other data with the data bus when the disk drive system is reading servo data. The other integrated circuit exchanges the user data with the data bus when the disk drive system is reading or writing the user data.

Abstract: A SCSI bus expander provides signal conditioning for transmitted data pulses that is particular to a negotiated data transfer rate. The expander monitors the bus arbitration to determine the devices involved in the transfer, and thereafter monitors the data transfer rate negotiations to determine the transfer rate to be used by that particular combination of devices. An indication of the transfer rate is stored in a memory device at an address determined by the device IDs. The transfer rate is then used to select tap values for tap lines that modify the pulse width and/or a propagation delay of the pulse, so as to correct for signal degradation and to align it better relative to other signals during data transmission. The specific tap values may vary for the different combinations of transmitting and receiving devices involved in the transfer, since the manner in which the pulse characteristics should be modified may be different for different transmission rates.

Abstract: A delayed start oscillator includes an oscillator enable signal having first and second states thereof for selectively enabling and disabling the oscillator respectively. An oscillator output signal has first and second levels thereof responsive to the first state of the oscillator enable signal for providing an oscillator output signal. A timing circuit is coupled to a supply voltage line for providing a timing signal output indicative of a selected delayed start duration and a plurality of series connected inverting stages are coupled to receive the oscillator output signal and the timing signal. The oscillator output signal remains at a first level for the delayed start duration in response to the timing signal and subsequently transitions between the first and second levels at an operational frequency determined by the plurality of inverting stages until the oscillator enable signal transitions to the second state thereof.

Abstract: A closed loop wire saw loop, a method for making the closed wire saw loop, and an apparatus and method for slicing a work piece, in particular, a polysilicon or single crystal silicon ingot, utilizing a closed loop of diamond impregnated wire in which the work piece (or ingot) is rotated about its longitudinal axis as the diamond wire is driven orthogonally to it and advanced from a position adjoining the outer diameter (“OD”) of the ingot towards its inner diameter (“ID”). In this manner, the diamond wire cuts through the work piece at a substantially tangential point to the circumference of the cut instead of through up to the entire diameter of the piece and single crystal silicon ingots of 300 mm to 400 mm or more may be sliced into wafers relatively quickly, with minimal ‘kerf” loss and less extensive follow-on lapping operations. The closed wire saw loop is made by squaring and welding the wire ends together and then twice heat treating the weld at about 1500 F.

Abstract: A system and method for hardware assisted formatted data transfer allows a formatting storage controller to read and record data on a formatted storage medium and avoids a requirement of continuous interaction by a host system in the transfer process. The host system can initiate the transfer process by sending a command block, a data definition, and an on-media structure definition to a formatting storage controller, which performs the formatted transfer and notifies the host system when the transfer is completed or an exception occurs. Alternately, the formatting storage controller can access one or more on-media structure definitions stored in a persistent storage unit in accordance with an on-media structure selector provided by the host system in the command block.

Abstract: An integrated circuit having a voltage source and a plurality of conductive power bus tiers extending across the integrated circuit. Each of the power bus tiers are electrically coupled in parallel to the voltage source. The integrated circuit includes a filter capacitor having a first plate and a second plate that are separated by a capacitor dielectric. The first plate forms a bus strap coupling to each of the plurality of power bus tiers.

Abstract: An enhanced bus turnaround integrated circuit dynamic random access memory (“DRAM”) device of particular utility in providing maximum DRAM performance while concomitantly affording a device with may be readily integrated into systems designed to use zero bus turnaround (“ZBT”), or pipeline burst static random access memory (“SRAM”) devices. The enhanced bus turnaround DRAM device of the present invention provides much of the same benefits of a conventional ZBT SRAM device with a similar pin-out, timing and function set while also providing improvements in device density, power consumption and cost approaching that of straight DRAM memory.

Abstract: A voltage down converter with hysteresis generator combining a hysteresis signal to a reference voltage and an output voltage feedback signal applied to a comparator. The hysteresis generator is coupled to a control signal giving advance notice of when a high current load is to be activated. The hysteresis signal is switched to a first state prior to the high current load activation, and switched to a second state after the high current load activation. In the first state, the hysteresis voltage is added to a reference voltage. In the second state, the hysteresis voltage is added to the voltage output feedback signal.

Abstract: A textured air bearing surface (“ABS”) slider design of particular utility in devices which utilize an air bearing surface to control the flying height or spacing between two relatively moving surfaces such as the sliders designed for use in conjunction with the read/write data transducer elements in a hard disk drive. The textured ABS slider provides much improved slider-to-media stiction and contact start stop (“CSS”) performance due to its provision of much earlier take-off characteristics which is of particular importance for use with high RPM drive designs which allow for higher data throughput. At low RPMs the fly height of the slider is increased while the fly height remains substantially the same at normal operating speeds. The textured ABS slider design disclosed may be readily effectuated with only minimal design and processing changes.

Abstract: A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer system contains the same line of memory which thereby reduces the searches required to perform the coherency operations and the overall size of the memory needed to support the coherency system. The technique includes the attachment of a “coherency tag” to a line of memory so that its status can be tracked without having to read each processor's cache to see if the line of memory is contained within that cache. In this manner, only relatively short cache coherency commands need be transmitted across the communication network (which may comprise a Sebring ring) instead of across the main data path bus thus freeing the main bus from being slowed down by cache coherency data transmissions while removing the bandwidth limitations inherent in other cache coherency techniques.

Abstract: A computer system is capable of recovering from a deadlock using communication gateway devices, such as a bridges, which each use a deadlock recovery mechanism. Rather than avoid deadlocks through constant monitoring of the communications path, the bridge allows the deadlock to occur. The recovery mechanisms of the bridges control the resolution of the deadlock. In one embodiment, the recovery mechanism within each bridge causes the local device which controls its bridge to disconnect. Additionally, the bridges terminate their requests for control of each other, thereby breaking the deadlock and allowing communications to resume. In another embodiment, the recovery mechanism within each bridge terminates the bridge's request for control of the other bridge. Additionally, the recovery mechanisms cause the bridges to become idle in accordance with a time delay value. The bridge with the shorter delay becomes active first and takes control of the communication path, thereby breaking the deadlock.

Abstract: A multi-layer ferroelectric thin film includes a nucleation layer, a bulk layer, and an optional cap layer. A thin nucleation layer of a specific composition is implemented on a bottom electrode to optimize ferroelectric crystal orientation and is markedly different from the composition required in the bulk of a ferroelectric film. The bulk film utilizes the established nucleation layer as a foundation for its crystalline growth. A multi-step deposition process is implemented to achieve a desired composition profile. This method also allows for an optional third composition adjustment near the upper surface of the film to ensure compatibility with an upper electrode interface and to compensate for interactions resulting from subsequent processing.

Abstract: A reference voltage generator for producing a reference voltage that is a preselected amount below a power supply voltage. A reference voltage source produces a first reference voltage that is VREF above the ground potential. A first load device coupled to the ground node and generates an internal reference signal that is determined by the magnitude of current flowing in the first load device. A differential amplifier produces a signal determined by a difference between the signals on the first and second inputs. A current regulating switch having a control node coupled to the differential amplifier output, and coupled to determine the current through the first load device. A second load device coupled in series with the first load device and coupled to the power supply node has an impedance selected to cause the second load device to generate the second reference voltage.

Abstract: A self calibrating zero compensation circuit for a fluxgate compass comprising a toroidal core; a drive winding coupled to said core, and at least one and preferably two secondary sensing windings coupled to said core comprises a continuously operating demodulator coupled to the sensing windings and an intermittently operated drive signal fed to the drive winding. A microprocessor is coupled to the demodulator output through an analog to digital converter. The microprocessor provides alternatingly to the drive winding a drive signal for a first period of time and prevents transmission of the drive signal for a second, preferably equal period of time. During the second period of time, the sensing windings and the demodulator provide an output signal to said microprocessor representing the zero signal reference. The demodulator output during the first period of time represents the magnetic field signal from the compass.

Abstract: A high speed output enable path and method for an integrated circuit device which effectively minimizes the gate delays in the critical integrated circuit device data and clock paths and in which most amplification is added in the reset path which is not critical to access time. Based on an external clock, several “one-shot” internal output enable clocks are generated. These parallel output enable clocks have select information embedded in them to facilitate the multiplexing of several different data paths onto a single output buffer. This select information is implemented ir the reset portion of the one-shot circuit thereby removing it from the critical portion for determining access time.

Abstract: The components used in the method comprise a heat-dissipating base plate, one or more three-layer plates (the top layer consisting of copper plates and strips) and a one-piece frame designed to constitute the terminals. After the chips have been soldered onto the upper plates and connected to the strips, the inner ends of the frame are soldered to points of connection with the chips. This is followed by the encapsulation in resin and the shearing of the outer portions of the frame, which, during the process, serve to temporarily connect the terminals.