Abstract: A highly precise range measurement instrument is made possible through the use of a novel and efficient precision timing circuit which makes use of the instruments internal central processing unit crystal oscillator. A multi-point calibration function includes the determination of a “zero” value and a “cal” value through the addition of a known calibrated pulse width thereby providing the origin and scale for determining distance with the constant linear discharge of capacitor.

Abstract: The invention includes a drive control integrated circuit with an intelligent and efficient tracing capability. The drive control integrated circuit executes operating instructions grouped into modules. The drive control integrated circuit stores the module numbers for executed modules in a memory. System designers can then retrieve the module numbers from the memory to assess the operation of the drive control integrated circuit. Some typical modules are read, write, seek, error, and servo modules. The drive control integrated circuit also stores operating parameters associated with the executed modules in the memory. Some typical operating parameters are instruction codes, head numbers, cylinder numbers, and error codes. The invention allows system designers to specify a particular trace operation and wait for the drive control integrated circuit to load the module numbers and operational parameters of interest into the memory.

Abstract: A system and method for accelerating web site access and processing utilizing a multiprocessor computer system incorporating reconfigurable and standard microprocessors as the web site server. One or more reconfigurable processors may be utilized, for example, in accelerating site visitor demographic data processing, real time web site content updating, database searches and other processing associated with e-commerce applications. In a particular embodiment disclosed, all of the reconfigurable and standard microprocessors may be controlled by a single system image of the operating system, although cluster management software may be utilized to cause a cluster of microprocessors to appear to the user as a single copy of the operating system.

Abstract: Apparatus, and an associated method, provides iconic representations of actions available to be performed upon an object of a particular datatype. The iconic representations are displayed, for instance, as part of a toolbar on a computer display. A representation of an object upon which an action is to be performed is dragged-and-dropped upon the iconic representation of the selected action to invoke that action upon both the dropped object and the object of a particular datatype.

Abstract: Methods and an apparatus for storing information in a processing device with flexible security are disclosed. In one embodiment, an apparatus processes back-to-back write and read operations without stalling the processor. A cache memory subsystem buffers write operations between a central processing unit (CPU) and the cache memory subsystem. Included in the cache memory subsystem are a tag memory, a data memory and a store buffer. The store buffer is coupled to both the data memory and the tag memory. Additionally, the store buffer stores a write operation.

Abstract: A boosting circuit for a ferroelectric memory using a NAND-INVERT circuit to control one electrode of a ferroelectric boosting capacitor. The other node of the capacitor is connected to the node to be boosted, which may be coupled to a word line. The NAND circuit has two inputs, one being coupled to the word line and another for receiving a timing signal. The timing input rises to initiate the boosting operation, and falls to initiate the removal of the boosted voltage. Only the selected word line in the memory array is affected as any word line remaining at a low logic level “0” will keep the inverter output clamped low. A second embodiment adds a second N-channel transistor in series with the inverter's N-channel transistor to allow for the option of floating the inverter output if it is desired to more quickly drive the word line high during its first upward transition.

Abstract: A variable width flat tape head for bi-directional contact recording and method for making the same has significant advantages over both traditional contoured tape heads and single width flat heads for contact recording applications. The variable width head and process disclosed herein allows for greater ease of manufacturing, efficient layout of the devices on thin film wafers and provides a significant cost reduction in the production of the head compared to traditionally contoured tape heads. In addition, the present invention reduces unnecessary surface area where the tape contacts the head, thus reducing tape wear and damage that is present in single width flat heads (where the tape is in contact uniformly across the tape width), thereby providing a concomitant improvement in tape wear and life.

Abstract: A method of patterning and etching an integrated circuit ferroelectric capacitor uses a layer of PZT which has the same composition as the capacitor PZT as a temporary encapsulation during PZT grain growth annealing. The temporary encapsulation PZT also serves as a hard mask to pattern the top electrode and the capacitor PZT layers for a capacitor-on-oxide structure, i.e., two-layer-one-step patterning. The process of the present invention can also be modified as a three-layer-one-step patterning process and can be applied to a capacitor-on-plug structure.

Abstract: A method for maximizing buffer usage in a disk drive system. Control circuitry within the disk drive system tansfers the defective sector list for the disk to a buffer, and places the list in a reserved list area. The size of the defective sector list is then determined and the reserved list area is reduced to a size equal to the size of the defective sector list plus some spare room. If the newly sized reserved list area is not at one end of the buffer, it is then moved to one end of the buffer to leave the remainder of the buffer as a contiguous and expanded reserved user area for use data. The expanded reserved user area reduces the time of read or write operations in a disk drive.

Abstract: A top surface imaging technique for top pole tip width control in a magnetoresistive (“MR”) or giant magnetoresistive (“GMR”) read/write head is disclosed in which a multi-layer structure is employed to define the thick photoresist during processing resulting in much improved dimensional control. To this end, a relatively thin upper photoresist layer is patterned with much improved resolution, an intermediate metal or ceramic layer is then defined utilizing the upper photoresist layer as a reactive ion etching (“RIE”) mask, with the intermediate layer then being used as an etching mask to define the bottom-most thick photoresist layer in a second RIE process. As a consequence, a much improved sub-micron pole tip width along with a high aspect ratio and vertical profile is provided together with much improved critical dimension control.

Abstract: A local write driver circuit for an integrated circuit device memory array which requires only a single write enable signal to couple complimentary data signals between global and local write data lines thereby obviating the need to provide complementary write enable signals as in conventional implementations. By eliminating the need for a second complementary write enable signal line, less on-chip die area is required for the signal path along with a concomitant reduction in power requirements due to the fact that there is one less line which has to switch during a given write cycle.

Abstract: A microcomputer comprises an integrated circuit device with processor and memory and communication links arranged to provide non-shared connections to similar links of other microcomputers. The communication links include message synchronisation and permit creation of networks of microcomputers with rapid communication between concurrent processes on the same or different microcomputers.

Abstract: A computer system having a memory system where at least some of the memory is designated as shared memory. A transaction-based bus mechanism couples to the memory system and includes a cache coherency transaction defined within its transaction set. A processor having a cache memory is coupled to the memory system through the transaction based bus mechanism. A system component coupled to the bus mechanism includes logic for specifying cache coherency policy. Logic within the system component initiates a cache transaction according to the specified cache policy on the bus mechanism. Logic within the processor responds to the initiated cache transaction by executing a cache operation specified by the cache transaction.

Abstract: A computer system and a method for operating a processor including the steps of establishing a first register save area and a second register save area in a memory, where each register save area holds data values that define a context. The first context is loaded in the processor by loading at least some of the data values from the first register save area into the plurality of registers. A first pointer value to the first register save area is stored in a current RFSA register. A context switch is indicated by storing a second pointer to the second register save area in the current RFSA register. The first pointer is transferred from the current RFSA register to a previous RFSA register. All of the data values that define the first context are transferred from the registers to a shadow register file. The second context is established in the processor by loading selected data values from the second register file save area into the plurality of registers.

Abstract: A method of and apparatus for displaying multiple, user preferentially linked pages of at least one document on a display screen adapted for Web or network viewing of pages of data by a browser program. This is accomplished by creating at least a template page having substantial portions thereof of user data and defining a first predetermined substantially static area on a display screen. A second predetermined static area on the template page is created to give the appearance of a window on the screen, the window having the capability of receiving a plurality of variable but user requested subsection of data therein, the subsections being linked to the template page and to each other. The user may choose a selectable control on the static portion of the display screen to permit the selection of specific linked subsections of data for viewing in the second predetermined static area on the template page.

Abstract: SYSTEM V utilities enable software developers to provide delivery of complex packages onto a UNIX operating system. An enhancement to the UNIX System V ABI format called class archive format enables sets of files to be combined into archives, these files being compressed or encrypted. The compressed/encrypted ABI package install with behavior defined in System V ABI. The class archive format allows a manufacturer to combine files from the ABI format reloc directory and root directory, into an archive directory. Class action format adds a directory called archive to the ABI format. Any class of files that are intended for archive is combined into a single file, and each file is then placed into the archive directory as class1, class2, etc. All files that are archived in this manner are removed from the standard ABI reloc directory and root directory, and an install class action script is placed into the scripts portion of the standard ABI install directory.

Abstract: A transmission line driver circuit that minimizes ringing effects while providing an acceptably fast output response. A plurality of increasingly powerful transistors are activated at different times to drive an output signal without ringing under low impedance conditions and quickly under high impedance conditions. The transmission line driver also includes a digital logic circuit. A strong inverter is connected to a digital logic unit. The strong inverter is activated when the first of two conditions is satisfied: 1) a feedback signal drops below a predetermined level; or 2) an output signal from a final delay is received by the output circuit. In this way, the strong driver will always contribute to driving the output signal, but will only do so when there is little likelihood of ringing.

Abstract: A multi-chip integrated circuit, and an associated method, provides an interface of substantially reduced levels of capacitance and inductance relative to conventional connections formed of bond wires. One of the chips of the integrated circuits comprises a memory device, such as a DRAM, and another of the chips of the integrated circuit is formed of a logic chip, such as a CPU or graphics controller. The memory chip is mounted upon the logic chip utilizing chip-on-chip technology. Because of the reduced levels of capacitance and inductance of the interface connecting the chips together, the resultant integrated circuit can be operated at increased speeds and at reduced levels of power consumption.

Abstract: An in-band method/apparatus whereby a host is enabled to secure predetermined operational information relative to predetermined ports of a fiber channel switch. A set command is generated at the host and sent in-band to the switch. The information content of the set command defines the ports for which operational-parameters are to be monitored. The information content of the set command also defines which operational parameters are to be monitored. In response to receiving the set command, the switch establishes statistical counters for monitoring port operational parameters in accordance with received operational parameter identifiers. An accept signal is then sent in-band to the host, and a time period of port monitoring begins. After a predefined time period has expired, the host sends a read command in-band to the switch. The switch now generates a monitor record in accordance with the count content of the statistical counters that were established in response to the set command.

Abstract: A sensor for determining the position of a movable object along a selected axis. The system includes a target positioned at a location aligned with the selected axis. An optical energy emitter is mounted on the movable object and has a beam dispersion greater than two degrees directed at the target. An optical energy receiver is mounted on the movable object and aligned to receive optical energy reflected by the target. The optical energy detector generates a receive signal indicating reception of the optical energy. A time of flight circuit coupled to the emitter and receiver generates a flight time signal indicating the elapsed time from emission of the optical energy to reception of reflected optical energy. A control circuit monitors the flight time signal and outputs a position signal indicating position of the movable object with respect to the target.