Abstract: A multi-step stud design and method for fabricating the same of special utility for producing closely packed interconnects in magnetic recording heads, particularly higher density magnetoresistive and giant magnetoresistive tape heads. The multi-step stud fabrication process and structure enables the achievement of significantly higher interconnect densities resulting in an increased number of channels per millimeter on a single computer mass storage device recording head. A resultant stronger encapsulation surrounding the stud further provides increased channel reliability. The improved uniformity of the photoresist aperture achieved for each step in the stud structure, and lower current spreading resistance because of the wider underlying stud base size, increases stud uniformity resulting in improved stud yields. This increased yield compared with conventional single step stud processes reduces cost, even with the additional photolithography and plating processes involved.

Abstract: A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.

Abstract: A packet-based dynamic random access memory (“DRAM”) device incorporating an on-chip row register cache which is functional to reduce the initial device latency, reduce “page miss” latency and reduce chip layout overhead by reducing bus sizes and the level of required multiplexing and demultiplexing compared to Rambus® Direct RDRAM™ (trademarks, of Rambus, Inc., Mountain View, Calif.) devices. In accordance with an embodiment of the present invention, the row register cache and a separate write path, or bus, are integrated into each DRAM bank serving to improve DRAM latency parameters and pipeline burst rate, The row register holds “read” data during burst reads to allow hidden precharge and same bank activation to minimize “page miss” latency. The faster pipelined burst rate simplifies Direct RDRAM multiplexer/demultiplexer logic and reduces internal data bus size by 50%.

Abstract: An octal transparent latch or D-type register (or flip-flop) integrated circuit device may be packaged in an industry standard logic pin-out and configuration but having nonvolatile properties such as automatically recording the output state in nonvolatile form and restoring it on power up. The nonvolatile memory elements are ideally ferroelectric capacitors, using well known ferroelectric materials such as PZT, SBT, or BST or other ferroelectric materials. EEPROM, Flash, SNOS, or other writeable nonvolatile technologies can also be used. In a particular embodiment disclosed herein, the nonvolatile elements of the integrated circuit device are written only when the latched state changes to reduce write endurance changes thereto and data changes on either the input or output data lines that are not latched have no effect.

Abstract: A system and method of compensating for non-linear voltage-to-delay characteristics in a voltage controlled delay line such as those used in delay-locked loop (“DLL”) circuits in integrated circuit (“IC”) devices such as double data rate (“DDR”) dynamic random access memory (“DRAM”), static random access memory (“SRAM”), processors and other IC devices. The technique renders the incremental changes for each correction to the control voltages to the voltage controlled delay line a function of the control voltage itself. The change in the control voltage becomes smaller as the control voltage gets lower thereby effectively precluding over-correction and excessive jitter.

Abstract: A head structure for writing data on a magnetic media including a first pole having an upper surface and a write gap covering a portion of the upper surface. An upper pole tip formed on the write gap having a first width. A second pole having a second width greater than the first width and coupling to an upper surface of the upper pole tip. A conductive coil magnetically coupled to the first pole and the second pole to induce magnetic flux within the first and second pole in response to a current flowing in the coil.

Abstract: A cache coherency directory for a shared memory multiprocessor computer system. A data structure is associated with each cacheable memory location, the data structure comprising locations for storing state values indicating an exclusive state, a shared state, an uncached state, a busy state, a busy uncached state, a locked state, and a pending state. The busy state and pending state cooperate to reserve a cache line for future use by a processor while the cache line is currently being used by one or more other processors.

Abstract: A storage system capable of selectively presenting logical units to one or more host computing systems. The storage system comprises one or more persistent storage devices arranged as logical units; an array controller controlling and coordinating the operations of the persistent storage devices; a memory accessible by the array controller; and a configuration table stored in the memory, the configuration table containing one or more entries governing the interactions between the logical units and the one or more host computing systems.

Abstract: In a system comprising an interconnect and a plurality of modules connected to the interconnect, a circuit for controlling which of said modules is able to put information onto said interconnect, said circuit comprising a store which stores status information for each module, said status information defining if the respective module is permitted to put information on said interconnect.

Abstract: This disclosure involves the combination of data compression and decompression with a virtual memory system. A number of computer systems are discussed, including so-called embedded systems, in which data is stored in a storage device in a compressed format. In response to a request for data by a central processing unit (CPU), the virtual memory system will first determine if the requested data is present in the portion of main memory that is accessible to the CPU, which also happens to be where decompressed data is stored. If the requested data is not present in the decompressed portion of main memory, but rather is present in a compressed format in the storage device, the data will be transferred into the decompressed portion of main memory through a demand paging operation. During the demand paging operation, the compressed data will be decompressed.

Abstract: The invention is a servo compensation method and system for use in a disk storage system. The disk storage system experiences error that causes a head to become mis-aligned with the disk. The error comprises multiple spin-frequency harmonic run-out error and other servo position errors. During follow mode, a digital filter processes a position error signal to generate a compensation signal. The position error signal is comprised of components representative of the multiple spin-frequency harmonic run-out error and the other servo position errors. The compensation signal is comprised of components that cause the servo positioning system to compensate for the multiple spin-frequency harmonic run-out error and the other servo position errors. The digital filter also operates as an oscillator that provides an oscillating signal at multiples of the spin frequency of the disk during seek mode.

Abstract: An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address.

Abstract: A low power consumption delay locked loop for integrated circuit devices wherein a wider frequency range of operation is achieved by matching the delay of the clock comparison function of the phase detector to the slow operating condition of the programmable delay. In a particular embodiment, this may be effectuated by incorporating at least one additional flip-flop section in the phase detector circuit and more than one such section may be utilized depending on the operating targets of maximum frequency and frequency range. By latching the phase detector outputs through the use of a fast/slow latch circuit, a minimum control pulse is defined which allows a unitized change on the voltage signals that control the programmable delay in a voltage controlled delay line. This also improves efficiency and reduces power consumption by eliminating switching current through transistors that control the voltage levels determining the programmable delay.

Abstract: A method for implementing a link level service in a computer network having a first port device and a second port device. Node identification data is stored in the second port device. A physical-layer communications coupling is provided between the first port device and the second port device which may be a point-to-point, loop, or switched circuit connection. The first port device sends a request node identification (RNID) message addressed to the second port device. The second port device creates an accept message and copies stored node identification data into the accept message. The second port device sends the accept message to the first port device.

Abstract: A profile service, instance is linked to a plurality of external data stores. Each external data store is associated with a predefined data store connector class that describes a connector object that establishes a link and provides methods to query the associated data store. An external data store profile is created in the profile service that names the connector class. An external data store reference object is created in the profile service instance that identifies the external data store profile and a number of parameters that specify particular data desired from the external data store. A profile within the profile service instance includes an attribute that names the data store reference object. When the attribute is evaluated, the data store reference object is instantiated, optionally using parameters specified at runtime, and passed as a parameter to an instance of the data store connector class identified by the external data store profile.

Abstract: A parallel data bus tester is particularly applicable to SCSI type buses, and uses a plurality of comparator circuits to simultaneously examine the voltages present on the conductors of a bus cable. For twisted pair type conductors, the tester uses a high reference voltage, which is compared to the high voltage conductor of each pair, and a low reference voltage, which is compared to the low voltage conductor of each pair. The reference voltages are adjustable, and allow each reference voltage to be swept through the expected voltage range for its respective conductors. As the level of a reference voltage crosses that of a conductor voltage being examined, a comparator that receives the reference voltage and conductor voltage changes output state. This output is used to drive a corresponding LED assigned to the conductor in question. Thus, as the reference voltage, which is compared to each of its corresponding conductor voltages (i.e.

Abstract: A hard disk drive is damped in order to reduce tracking errors by isolating the drive from the enclosure it is mounted in using one or more pieces of adhesive viscoelastic material. The hard disk drive is mounted by means of a secondary mounting plate having ventilation holes. Vibrations introduced into the drive from the enclosure, as well as rotational vibrations introduced by the rotation of the drive itself, are substantially damped by the viscoelastic material. As a result, tracking errors are substantially reduced.

Abstract: Disclosed is an optical sensor used for remote laser level monitoring in liquid storage vessels. The sensor is mounted directly to a standard tank nipple, located on top of the vessel, by a threaded connecting means and is linked to a laser measurement device via fiber optic cabling. The level in the vessel is measured as a function of the time required for a laser signal to be transmitted from the sensor, reflected off the liquid surface and returned to the receiver lens located in the sensor.

Abstract: An enhanced memory algorithmic processor (“MAP”) architecture for multiprocessor computer systems comprises an assembly that may comprise, for example, field programmable gate arrays (“FPGAs”) functioning as the memory algorithmic processors. The MAP elements may further include an operand storage, intelligent address generation, on board function libraries, result storage and multiple input/output (“I/O”) ports. The MAP elements are intended to augment, not necessarily replace, the high performance microprocessors in the system and, in a particular embodiment of the present invention, they may be connected through the memory subsystem of the computer system resulting in it being very tightly coupled to the system as well as being globally accessible from any processor in a multiprocessor computer system.

Abstract: A method, and associated apparatus, for eliminating pulse width variations in digital delay lines. The method includes partitioning the delay line into two substantially identical blocks of delay inverters and inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated, and the parasitic loading of the inverter between the blocks and the inverter on the output of the second block is the same. Since the rising edge input to the first block becomes a falling edge input to the second block as it propagates through the delay line, the rising and falling input edges will encounter an identical set of transitions as they propagate through the two blocks.