Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.

Abstract: A shared sense amplifier driver technique for integrated circuit devices including an array of memory cells comprises a plurality of sense amplifiers couplable to the memory cells with each of the sense amplifiers having an associated pull-up and pull-down switching device respectively coupled to a first and second latch node thereof. A first subset of the plurality of sense amplifiers have their first latch node (e.g. latch P-channel “LP”) electrically coupled and a second differing number subset of the plurality of sense amplifiers have their second latch node (e.g. latch N-channel “LN”) electrically coupled. By sharing the selected LP and LN nodes with more than one sense amplifier in a column, “write” recovery time can be significantly improved over that of conventional layouts and designs.

Abstract: A logic circuit has two internal voltage lines and includes additional upper and lower MOS transistors for coupling the external voltage supplies to the internal voltage nodes instead of using a single diode or transistor. These additional devices serve to clamp the internal voltages to a level that minimizes leakage current and maintains the data in the logic circuits.

Abstract: A method and computer program product for managing and manipulating user-defined and system databases in a computing system. A database interface, which can be a graphical user interface, accesses a database configuration file containing descriptions of the contents of each of the databases. The database interface interprets the contents of each database in accordance with the configuration file, and provides for user access and manipulation of the contents of the databases.

Abstract: A programming environment including a source code programming language comprising a plurality of programming constructs. A first set of constructs within the programming language are for expressing procedural operations performed on specified data. A second set of constructs within the programming language are for expressing complex data relationships of the specified data. A compiler receives programmed source code comprising user-selected and arranged portions of the first and second set of constructs and generating machine readable code capable of implementing the procedural operations and complex data relationships expressed by the source code.

Abstract: A method for secure data communication with a mobile machine in which a data packet is received from the mobile machine having a particular network address. A pool of secure addresses is established and a data structure is created to hold address translation associations. Each association is between a particular network address and a particular one of the secure addresses. If the received data packet is a secure data packet an association between the received data packet's network address and a secure address in the data structure is identified and the data packet's network address is translated to the associated secure address before forwarding the data packet on to higher network protocol layers. When the received data packet is not secure it is passed it on without address translation to the higher network protocol layers. For outgoing packets addressed to a secure address, the secure address is translated to a real network address (e.g.

Abstract: A method and system for hiding DRAM cycle time behind burst read and write accesses. A combined read and write data transfer area interacts with a set of sense amplifiers to accelerate read and write cycles. By independently isolating the read data transfer areas and the write data transfer areas, data can be transferred (1) from the DRAM array to the read data transfer areas, (2) from the write data transfer areas to the DRAM array, and (3) from the write data transfer areas to the read data transfer areas.

Abstract: An improved integrated circuit area efficient redundancy multiplexer circuit technique provides similar functionality to conventional CMOS transmission, or “pass” gates while concomitantly reducing circuit complexity, the die area necessary to support redundant elements and complementary control signals in memory device ICs and undesired parasitic capacitance. The technique of the present invention effectuates this end by utilizing the on-chip boosted voltage levels (Vpp) which are generally available in integrated circuit memory devices to supply the voltage for the control signal applied to a single N-channel transistor pass gate instead of the conventional supply voltage level of Vcc. The Vpp voltage and circuit ground (“GND”) are then utilized as the logic “high” and “low” signal levels respectively. This use is made possible due to the fact that these control signals operate at a direct current (“DC”) level after device power-up.

Abstract: A method for fabricating integrated capacitors, of particular utility in forming a ferroelectric capacitor array for a ferroelectric memory integrated circuits, begins with provision of a substrate. The substrate is typically a partially-processed CMOS integrated circuit wafer coated with an adhesion layer. Upon the substrate is deposited a bottom electrode layer, typically of noble metal, a dielectric layer, typically doped PZT, and a top electrode layer, typically a noble metal oxide. Next is deposited a hardmask layer of strontium ruthenium oxide, followed by a photoresist layer. The photoresist layer is aligned, exposed, developed, and cured as known in the art of integrated circuit photolithography. The resulting stack is then dry etched to remove undesired portions of the hardmask layer, the top electrode layer, and the dielectric layer. A principle advantage of the process is that a single photomasking operation is sufficient to define the top electrode and dielectric layers.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A method and system for laying out and accessing data in a disk drive system. The layout resides in a table in firmware of the disk drive system. The table includes multiple entries or rows, one corresponding to each different area in the disk media. The entry provides information about the range of block addresses in that area including the starting and end block address in the area, and information about the range of physical addresses including the head and the starting and ending cylinder number. A firmware routine finds the appropriate entry in the table and converts the block address to the physical address, or vice versa.

Abstract: A system and method for eliminating pulse width variations in digital delay lines partitions a delay line into two substantially identical blocks of delay inverters, inserting a first inverter between the two blocks and a second substantially identical inverter at the output of the second block. The requirement for matching device characteristics at the individual delay inverter level is eliminated and the only requirement is that the parasitic loading of the inverter between the blocks and the inverter on the output of the second block be the same. Consequently, the layout of the delay inverters in a single block may be made in the most efficient manner possible and the same identical layout can be used for the first and second blocks.

Abstract: A system, method and computer program product for searching for, and retrieving, profile (or directory) attributes based on other attributes of the target profile and that of associated profiles. In a specific implementation, the LDAP RFC 2254 string search syntax may be utilized to allow multiple related search filters to be specified at one time. The first of the sequence of query strings defined is used as a filter to retrieve candidate results and the succeeding filters, or query strings, are used to determine if a specific profile or directory should even be considered.

Abstract: A computer implemented system, method and computer program product for automatically distributing copies of a replicated database for a computer system comprising at least first and second host computers. Each of the host computers operatively control at least one associated computer mass storage device controller coupled to commonly accessible computer mass storage devices by at least one storage device bus. The system and method comprises the step of enumerating each of the various host computers of the computer system, each of the computer mass storage device controllers associated with each host computer and each of the computer mass storage devices coupled to the storage device buses coupling the controllers.

Abstract: A system and method for effectuating distributed consensus among members of a processor set in a multiprocessor computing system that is effective even when only a single surviving processor is operational and is achieved through joint implementation of a virtual state machine utilizing a sequence of numbered input commands. System synchronization is achieved by having all of the processors agree on the sequence of input commands so that they execute the same virtual state machine. Input commands are numbered consecutively and the processors use a set of shared stores (e.g. disk drives) to communicate amongst themselves requests (i.e. ballots) for new state machine inputs (or commands) and state machine inputs that have already been chosen (i.e. committed commands). A consensus process is used to decide upon (or commit) each command and this consensus is achieved using a majority of known system stores rather than a majority of known processors.

Abstract: An implementation of 1T/1C nonvolatile ferroelectric RAMS without using any reference cells—the polarization state in a memory cell is determined by applying two consecutive plate pulses on the ferroelectric capacitor in the memory cell, preamplifying the bit line voltages corresponding to these two plate pulses, and comparing the preamplified voltages. The two consecutive plate pulses have the same polarity.

Abstract: A data bus architecture for integrated circuit embedded dynamic random access memory (“DRAM”) having a large aspect ratio (length to width ratio) which serves to reduce power requirements in the data path through the use of multiple metal layers to reduce capacitance on the data busses. This architecture is particularly advantageous for use in addressing data bussing problems inherent in integrated circuit devices having embedded DRAM with a large aspect ratio as well as a relatively large number of input/outputs (“I/Os”) which must be located along one narrow side of the memory. In accordance with the present invention, the memory is divided into multiple sections with data bussing in those sections routed in one metal, or conductive, layer. A different metal layer is used to route global data across these sections to a data register located on one edge of the memory.

Abstract: A system, method and computer program product for hardware assisted backup for a computer mass storage subsystem wherein files to be backed up from a source storage medium (e.g. disk) to a formatted storage medium (e.g. tape) are written in logical block number (“LBN”) order regardless of the file's on-disk layout. If the source file structure information is available it is used or the disk blocks containing the file structure are marked in a used (or “free”) block bit map which may then be modified to exclude files that are “open for write”, marked as “no backup” or not part of the selected file save operation. In operation, the blocks are written to tape using a Tape Copy Data (“TCD”) command. Blocks that were selected, but excluded as “open for write” may then be written to the tape utilizing more conventional methodologies.

Abstract: A method of chemical-mechanical polishing for forming a shallow trench isolation is disclosed. A substrate having a number of active regions, including a number of relative large active regions and a number of relative small active regions, is provided. The method comprises the following steps. A silicon nitride layer on the substrate is first formed. A number of shallow trenches are formed between the active regions. An oxide layer is formed over the substrate, so that the shallow trenches are filled with the oxide layer. A partial reverse active mask is formed on the oxide layer. The partial rever active mask has an opening at a central part of each relative large active region. The opening exposes a portion of the oxide layer. The opening has at least a dummy pattern. The oxide layer on the central part of each large active region is removed to expose the silicon nitride layer. The partial reverse active mask is removed. The oxide layer is planarized to expose the silicon nitride layer.

Abstract: A FRAM configurable output driver circuit allows the user to configure the output driver for either CMOS level push/pull operation or true open drain operation. This configuration is stored in a non-volatile memory including a FRAM cell and a standard logic latch. The configuration data is restored to the latch on powerup. The user is able to change the configuration at any time. Any changes to the configuration are stored in the non-volatile memory.