Abstract: The present invention provides a fluid delivery system for delivering fluid for a semiconductor manufacturing operation using a sensor to monitor fluid flow and stop fluid flow when gas bubbles or uneven fluid flow occurs. The system comprises: a fluid container 10 connected to a pressurized gas supply 18 by a gas supply tube 17; the fluid container 10 connected to a fluid feed tube 16; the fluid container 10 partially filled with a fluid 12; the fluid feed tube 16 having an inlet end 16A and an outlet end 40; a stop valve 20 connected in the fluid feed tube 16 between the fluid container 10 and the outlet end 40; an optical sensor 30 connected to the fluid feed tube 16; a control computer 39 for actuating the stop valve based on the analysis of the fluid by the optical sensor. The fluid flows from the fluid container 10 onto the wafer 50. The optical sensor 30 monitors the flow of the fluid and stops the flow of fluid when the fluid flowing past the optical sensor 30 contains gas bubbles or flows unevenly.

Abstract: A method of rapid thermal annealing (RTA) a TEOS oxide layer 50 that underlies a silicon nitride stop layer 60. The RTA of the TEOS-Oxide ILD layer 50 prevents the nitride stop layer 60 and oxide ILD layer 50 from peeling in subsequent thermal steps. The process comprises providing a semiconductor structure 10 with an uneven surface; forming an interlevel dielectric layer 50 composed of PE-TEOS oxide over the structure 10; rapid thermal annealing (RTA) the third interlevel dielectric layer 50 at a temperature between about 850 and 1015.degree. C. for a time between about 10 and 50 seconds; depositing a silicon nitride layer 60 over the third interlevel dielectric layer 50; and planarizing the silicon nitride layer 60 and the third interlevel dielectric layer 50.

Abstract: The present invention provides a method of manufacturing a read only memory that is code implanted late in the process after the first level metal thus reducing the turn around time to ship a customer order. The invention comprising the steps of: forming bit lines 125 and word lines 160 in a cell area 12A and MOS transistors in a peripheral area 13 of an integrated circuit; forming a first dielectric layer 300 over the surface; etching back the first dielectric layer 300 in the cell area; forming metal contacts 700 to the MOS devices in the peripheral areas 13; forming the second dielectric layer 320 over the resultant surface, storing the integrated circuit; and programming the ROM region 12A by the steps of forming a Code mask 340 with openings 340A from over portions of word lines in the cell area and implanting impurities through the openings 340A into substrate under the selected word lines 160 thereby programming the ROM device.

Abstract: A method of stripping photoresist and polymer from a wafer after a dry etch of a nitrade or a polysilicon layer that immerses the wafer in a peroxydisulfate (S.sub.2 O.sub.8.sup.2-)/HCl wet bath and while the wafer is still immersed, irradiates the wafer with a UV laser. The method comprises: (a) forming an silicon nitride layer 24 and a photoresist pattern 28 over a semi conductor structure 10; (b) dry etching the silicon nitride layer 24 thus forming a polymer 30 over the photoresist pattern, and the silicon nitride layer, (c) Immersing the substrate, the photoresist pattern, the polymer 30 in a liquid bath 34 comprising (1) peroxydisulfate (S.sub.2 O.sub.8.sup.2-), (2) HCl, and (3) water; and irradiating the photoresist pattern 28 and polymer layer 30 with a UV laser thereby removing the photoresist 28 and polymer 30.

Abstract: A method to form a "mushroom shaped" gate structure 18 22 44A 70 that increases the top gate silicide contact area and improves the salicide process, especially TiSi.sub.2 salicide. The novel upper gate extensions 44A increase the top gate surface area so that the silicide gate contacts 70 will have a low resistivity. The invention includes forming a gate stack 18 22 26 comprised of a gate oxide layer 18, a center gate portion 22 and a hard mask 26. Next, we form a first insulating layer 40 over the gate stack 22 26 18. The hard mask 26 and a first thickness of the first insulating layer 40 are removed to expose sidewalls of the center gate portion 22. A second conductive layer 44 is formed over the first insulating layer 46 and the center gate portion 22. The second conductive layer 44 is etched to form critical rounded upper gate extensions 44A on the sidewalls of the center gate portion 22. Lower rectangular sidewall spacers 52 are formed on the sidewalls of the center gate portion 22.

Abstract: The present invention provides a method of removing photoresist from a wafer surface having a bonding pad using a three step clean composed of (1) a wet cleaning the substrate, (2) a F-containing gas high temperature plasma treatment which prevents the corrosion of aluminum contact pad, and (3) completely striping the photoresist strip using an O.sub.2 dry ash. The invention eliminates metal bonding pad corrosion and the completely removes residual photoresist from keyholes.

Abstract: A method of for aligning step and repeat reticle images for 2 adjacent sliders for magnetoresistive (MR) devices. The invention forms 3 wafer alignment targets for two adjacent sliders . The 3 wafer alignment targets are used to align adjacent reticle exposure fields. An novel common alignment target is between the two sliders. The stepper alignment system uses the wafer alignment target placed in the field stitch area between two adjacent fields and the alignment target for that particular field to align the reticle. The method includes: forming (1) a first wafer alignment target in the first slider area; (2) a second wafer alignment target in the second slider area; and (3) a center wafer alignment target between the first and the second wafer alignment targets. Using a stepper, exposing the first slider area with the reticle image field. The first reticle image field having spaced first and second reticle alignment keys.

Abstract: An heat treatment (anneal) process is provided that reduces stress in a metal layer structure having ARC TiN layer overlaying an aluminum layer formed in a high temperature process. An metal layer 32 composed of Al/Cu/Si is sputtered at a temperature of about 505.degree. C. on a semiconductor structure 10. Next, an ARC TiN layer 34 is deposited over the metal layer 32. In an important process, a heat treatment (anneal) is performed on the metal layer 32 and the ARC TiN layer 34. The heat treatment comprises three steps. First, a ramp up step is performed wherein the temperature is increased from room temperature to a temperature of about 450.degree. C. at a rate of about 40.degree. C./sec. Second, a temperature hold step is performed where the temperature is held at about 450.degree. C. for a time of about 30 seconds. Third, a ramp down step is performed where the temperature is ramped down at rate in a range of between about 8 and 10.degree. C./sec to room temperature.

Abstract: The invention provides a combination of a nozzle and a vacuum hood. The vacuum hood has a chamber that surrounds the tip of the nozzle and removes residue from the tip by a vacuum which flows in the chamber past the nozzle tip. This vacuum catches and removes residue from the nozzle tip and prevents the reside from interfering with the spraying action or dripping down. The method of the instant invention provides for dispensing a fluid from a nozzle without dripping fluid from the nozzle having a vacuum hood. The method comprises: (a) dispensing a fluid on a rotating semiconductor wafer through a nozzle over the wafer; (b) terminating the fluid flow through the nozzle; (c) creating an upward flow of gas about the dispensing nozzle when the flow of fluid through the nozzle is terminated; (d) capturing any fluid residue from the nozzle in the upward flow of gas; (e) removing the wafer and positioning another wafer; and (f) terminating the upward flow of gas; and repeating the process of steps (a) through (f).

Abstract: A method of forming an etch stop layer 40 above a fuse 16 in a fuse opening (or window) 92 using a specialized 2 stage etch process. The invention has two important features: First, the etch stop layer 40 is formed from a polysilicon layer (P2 or P4) that is used to fabricate semiconductor devices on a substrate. The etch stop layer 40 is preferably formed of polysilicon layer to is used to from a contact to the substrate 10 (P2) or to form part of a capacitor (P4). Second, a specialized two stage etch process is used where the second stage etches the etch stop layer 40 while simultaneously forming a passivation layer 114 over a metal pad 85.

Abstract: A new method of metallization using a dimple free tungsten plug is described. An insulating layer is deposited overlying semiconductor device structures. An opening is etched through the insulating layer to contact one of the semiconductor device structures. A layer of tungsten is deposited overlying the insulating layer and within the opening. A photoresist block is formed on the tungsten layer over the contact opening. The photoresist block is a reverse pattern of the photoresist layer used to define the opening in the insulating layer. The tungsten layer is partially etched forming a mound in the tungsten layer under the photoresist block and over the opening. The photoresist block is removed and the remaining tungsten layer is etched again resulting in the formation of a dimple free tungsten plug with a planar surface.

Abstract: The present invention provides a structure and method of forming a butting contact having protective spacers 50A that prevent shorting between a second polysilicon layer 60 and the substrate in a hole 20A in a isolation region 20. The following are provide: a isolation region 20, a first conductive line 30B over portions of the isolation region 20, and an inter-poly insulating layer 40. The protective spacers prevent shorts when the first conductive line 30B is misaligned and exposes a first portion of the isolation region 20 in a butt contact opening. A first photoresist layer 44 having a butt contact photoresist opening 44A over the first doped region 26 and over a first portion of the isolation is formed. The inter-poly insulating layer 40 is etched through the butt contact photoresist opening 44A and etches the first portion of the isolation region forming an isolation hole 20A. In an important step, protective spacers 50A are formed on the sidewalls of the isolation hole 20A.

Abstract: The present invention provides a structure and method for forming a moisture barrier guard ring structure 38 44 48 52 54 for around a fuse window 30 in a semiconductor device. The invention begins by forming a fuse structure 32 33 34 over the isolation regions cross the fuse window area. A cap layer 38 and an interlevel dielectric layer (ILD) 40 are formed over the fuse structure. A first annular ring 44 (e.g., contact w-plug) is formed over the isolation region 20 surrounding the fuse window area 30 and over the fuse structure 32 33 34. A key feature is that the first annular ring 44 and the cap layer 38 form a moisture proof seal over the fuse structure. A first conductive wiring line 48 is formed over the first annular ring 44. Next, an inter metal dielectric (IMD) layer 50 is formed over the interlevel dielectric layer 40. A second annular ring 52 is formed through the inter metal dielectric layer 50 on the first conductive wiring line 48.

Abstract: An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.

Abstract: An apparatus for producing thin film coatings and/or dopant levels on semiconductor wafers or other substrates with improved film growth uniformity (of thickness and composition) and/or dopant uniformity is provided. The apparatus is positioned in a furnace tube between the wafers and a gas inlet. The apparatus comprises a conical shaped baffle.

Abstract: A method of removing a planarized insulating layer from over an alignment mark on a wafer. The invention allows steppers to see alignment marks without the difficulty of viewing the alignment marks through the insulating layer overlying the alignment marks. The method begins by chemical mechanical polishing a conformal oxide layer over a substrate. Next, a first photoresist layer is formed over the conformal oxide layer. Then vias are etched in the conformal oxide layer in the device area and etch the conformal oxide layer in the alignment mark area. Subsequently, we form a second photoresist layer over the first photoresist layer and the conformal oxide layer. The second photoresist layer filling the vias, but not the alignment mark resist opening. Then etch the second photoresist layer leaving sidewall spacers on the sidewall of the first photoresist layer in the alignment mark area and leaving photoresist plugs filling the vias.

Abstract: A method to form, in a NMOS area, a shallow trench isolation (STI) having B doped sidewalls regions 44 to reduce the NMOS reverse narrow width effect in narrow active areas 12N (e.g., narrow channel regions <0.1 .mu.m wide). A substrate is provided having a NMOS area 13 and a PMOS area 15. A pad oxide layer 20 and a barrier layer 22 are formed on the substrate. Trenches 24 are etched in the substrate 10 in the NMOS and PMOS areas. The etching forms narrow active areas 12N and wide active areas 12W. The narrow active areas 12N have a width between 0.4 and 1.0 .mu.m. A liner layer 30 is grown on the sidewalls and bottom of the trench on the substrate. A first photoresist layer is formed covering the PMOS areas and having first opening over the NMOS areas. In a critical step, a large angle Boron implantation is performed into the sidewalls and the bottom of the trenches forming Boron doped regions 44 in the substrate. The first photoresist layer is removed.

Abstract: The present invention provides a structure and a method of fabricating a thermoelectric Cooler directly on the backside of a semiconductor substrate. The thermoelectric (TE) cooler (thermoelectric cooler) disperses heat from an integrated circuit (IC) that is formed on the front-side of the silicon substrate. Spaced first bonding pad holes 28 are formed in the backside of a substrate that expose bonding pads 24. Second holes 32 are formed between the spaced first bonding pad holes 28. A first insulating layer 34 is formed over the backside of the substrate, but not over the bonding pad 24. A metal layer is formed lining the first bonding pad holes 28. A polysilicon layer 46 is formed over the surface of the backside of the substrate in the second holes. The polysilicon layer is implanted thereby forming alternating adjacent N and P doped sections 46p 46n in the second holes. The adjacent N and P doped polysilicon sections 46n 46p are electrically connected to the bonding pads 24 by the metal layer 38.

Abstract: A crown capacitor for a memory device is formed using (1) an important early poly plug 42 process and (2) an etch barrier layer 34. A first insulating layer 30 and an etch barrier layer are formed over device structures and the substrate 10. A node contact hole 40 is formed through the etch barrier layer 34 and the first insulating layer 30. A plug 42 is formed filling the node contact hole 40. Next, a planarizing layer 44 is formed over the etch barrier layer 34 and the plug 42. A crown hole 46 is formed in the planarizing layer 44 exposing the plug 42. A first polysilicon layer 50 is deposited over the etch barrier layer, the plug 42, and the remaining first planarizing layer 44A. A Sacrificial layer 54 is formed over the first polysilicon layer 50 thereby filling the crown hole 46. The sacrificial layer 54 and the first polysilicon layer 50 are etch back to remove the exposed portions of the first polysilicon layer 50 over the planarizing layer 44A.

Abstract: The present invention provides a method of fabricating fully dielectric isolated silicon (FDIS) by anodizing a buried doped silicon layer through trenches formed between active areas to form a porous silicon layer; oxidizing the porous silicon layer through the trenches to form a buried oxide layer; and by depositing a dielectric in the trenches. The process begins by forming a buried doped layer in a silicon substrate defining a silicon top layer over the conductive buried doped layer. The silicon top layer and the buried doped layer are patterned to form trenches that extend into but not through the buried doped layer. The trenches define isolated silicon regions. The buried doped layer is anodized to form a porous silicon layer. The porous silicon layer is converted into a buried oxide layer by oxidation. The oxidation step also forms a liner oxide layer on the tops and sidewalls of the isolated silicon regions.