Abstract: The invention is an improved process for forming isolations of uniform thickness in narrow and wide trenches. The process begins by forming a pad layer on a semiconductor substrate. A first barrier layer is formed on the pad layer. The first barrier layer and pad layer are patterned forming openings, thereby exposing the substrate surface. The substrate is then etched through the openings to form shallow trenches in the substrate. The trenches generally falling into two ranges of width: narrow trenches having widths in the range between 0.3 .mu.m and 1.0 .mu.m; and wide trenches having widths greater than 1.0 .mu.m. A thin oxide film is grown on the sidewalls and bottoms of the trenches. A gap-fill dielectric layer is formed on the thin oxide film. A polysilicon layer is grown on the gap-fill dielectric layer. The polysilicon layer acts as a stop during CMP, providing additional protection of the gap-fill dielectric layer in the wide trenches. A planarizing material layer is formed on the polysilicon layer.

Abstract: A method of forming a wide top spacer (50 20S 40A) that prevents salicide bridging. The wide top spacer (50) consists of a first spacer (20S) and an upper spacer (40A) (half spacer). The upper spacer (40A) is formed by covering the first spacer with a sacrificial layer (30) and forming the upper spacer (40A) on a top portion of the first spacer. During a subsequent salicide process, the upper spacer (40A) prevents sputtered metal (60) from forming of an area (51) on the first spacer under the upper spacer (40A). This prevents shorting between the S/D (12) and the gate (18).

Abstract: The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220.

Abstract: The method for forming a "U" shaped floating gate 120a with high vertical projections 120c, begins by forming a dielectric layer 110 over the substrate 100. A photoresist layer 112 is then formed on the dielectric layer 110 and patterned to form a first opening 113. The first opening 113 exposes the dielectric layer 110. In an important step, a polymer layer 114 is formed over the photoresist layer 112 and on the vertical sidewalls of the first opening 113 thereby forming a second opening 115. The second opening 115 has a smaller width than that of the first opening 113. The dielectric layer 110 is anisotropically etched thru the second opening 115 thereby forming a third opening 116 in the dielectric layer 110. The photoresist layer 112 and the polymer layer 114 are now removed. The exposed substrate within the third opening 116 is thermally oxidized to form a tunnel oxide layer 118. A first polysilicon layer 120 is formed conformally on the resultant surface and in the third opening.

Abstract: The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specially designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas.

Abstract: The present invention provides a structure and a method of forming a stepped trench oxide structure for a semiconductor memory device. The stepped trench oxide structure has "oxide steps" (e.g., 252 or 34A, 34B, 34C) in the gate oxide 20 surrounding the tunnel oxide layer 30. The oxide steps 34 are formed where the oxide thinning effect normally thins the tunnel oxide 30 around the perimeter of the tunnel oxide layer 30. The oxide steps 34 252 compensate for the oxide thinning effect and eliminate the problems associated with the oxide thinning effects. The oxide steps are preferably formed using one photo mask to form two different sized openings using different photoresist exposure times. The preferred method comprises forming a first tunneling opening 220A in a first (gate) oxide layer 220. Then, forming a second oxide layer 250 over said exposed substrate and said first oxide layer 220.

Abstract: A structure and method for fabricating an ESD device for FET transistors by forming a silicon germanium region 40 under a channel region 44 of a field effect transistor (FET). The silicon germanium region 40 comprises the base of a parasitic bipolar 200 transistor that increases the turn on speed. The method comprises:a) forming a gate dielectric layer 20 over a substrate 10;b) forming a gate 30 over the gate 30; the substrate having a channel region under the gate; the channel region extending from the surface of the substrate to a channel depth below the substrate surface;c) forming a silicon germanium region 40 under the channel region 44 using a tilt angle ion implant of Germanium ions;d) forming source and drain doped regions 50 70 adjacent to the channel region and the silicon germanium region whereby the silicon germanium region comprises a base of a parasitic bipolar transistor 40.

Abstract: The present invention provides a method of forming a Self-aligned contact with fewer process steps. The invention includes a three step insitu process of (1) a first descum step, (2) a dry etch step and (3) second descum step followed by (4) an isotropic etch step. The process comprises coating, exposing, and developing, and baking a photoresist layer over an insulating layer. In an important process stage, three steps are performed: (1) an insitu first descum step, (2) a dry etch step and (3) a second descum step. The dry etch step forms a first self-aligned contact opening. Next, the first contact opening is isotropically etched forming a smoother second contact opening 44. The photoresist layer 30 is then removed. Lastly, a metal layer 60 is deposited in said second self aligned contact opening 44. The invention reduces cycle time and eliminates several process steps while maintaining high yields. The smoother second contact opening 44 provides better metal adhesion.

Abstract: The invention provides an index of line balance method for maintaining optimum queued quantities of products at a manufacturing step and over an entire manufacturing line. The method begins by: first, assigning a daily standard move of product (Std Move) which should be produced in a manufacturing line. Second, the standard WIP StdWIP is calculated for each manufacturing stage i by multiplying the theoretical cycle time C/T of each stage by the daily standard move StdMove; (i.e., StdWIP=CT*StdMove). Third, the difference Di between the current WIP CWi and standard WIP StdWIP at every stage i. (Di=Cwi-Swi, ) is calculated. Fourth, the cumulative difference CDi between current WIP Cwi and standard WIP StdWIP of every stage i from stage i to stage n is calculated. ##EQU1## Fifth, the index of line balance BIi is calculated by dividing the sum of all positive CDi from stage i to stage n by the absolute value of the sum of all negative CDi from stage i to stage n.

Abstract: An improved structure and method of forming a protective layer over an opening in insulation layers over a fuse is presented. The protective layer prevents contaminates from entering the exposed insulation layers in a fuse opening while not interfering with the laser trimming of the fuse. An opening through the layers over a fuse is made forming vertical sidewalls which expose portions of the insulation layers. A protective layer is formed over the insulation layer, the sidewalls and fuse thus preventing contaminates from diffusing into the exposed insulation layers. A second opening is made in the protective layer over the fuse link to allow a laser beam to melt the underlying fuse link.

Abstract: The present invention provides a structure and a method of manufacturing a resistor in a semiconductor device and especially for a resistor in an ink jet print head. The method begins by providing a substrate 10 having a field oxide region 20 surrounding an active area. The field oxide region 20 has an ink well region 52. Also a transistor is provided in the active area. The transistor comprises a source 12, drain 14 and gate electrode 16 18 19. A dielectric layer 24 is formed over the field oxide region 20 and the transistor 12 14 16 18. The dielectric layer 24 has contact openings over the source 12 and drain 14. A resistive layer 26 27 is formed over the dielectric layer 24 and contacting the source 12 and drain 14. The resistive layer 26 27 is preferably comprised of two layers of: a Titanium layer 26 under a titanium nitride 27 or a titanium layer 26 under a tungsten nitride layer 27. A first metal layer 28 is formed over the resistive layer.

Abstract: The present invention provides a method of manufacturing a lightly doped drain (LDD) structure using a polymer layer to define the LDD. The polymer layer is formed in an etch step which defines the gate electrode. The method begins by forming spaced field oxide regions 12 in a substrate 10. Next, a gate oxide layer 14, and a material layer 18 and a hard mask layer 22 are sequentially formed over the active area and the field oxide regions 12. A photo resist block 24 is formed over the hard mask layer 22 over the active area. The hard mask layer 22 is etched using the photo resist block 24 as a mask forming a hard mask block 22. The etch simultaneously forms a polymer layer 26 over the a top and sidewalls of the photo resist block 24 and over the sidewalls of the hard mask block. Impurities ions are implanted into the substrate in the active area using the polymer layer 26 as a mask forming highly doped drain regions 30 in the substrate 10. Next, the photo resist block 24 and the polymer layer 26 are removed.

Abstract: The present invention provides a method of forming a contact structure comprised of a silicon substrate, a titanium silicide layer, a barrier layer (i.e., TiN or TiNO), and a metal layer (e.g., Al or W). There are three embodiments of the invention for forming the titanium silicide layer and two embodiments for forming the barrier layer (TiN or TiNO). The first embodiment for forming a TiSix layer comprises three selective deposition steps with varying TiCl4:SiH4 ratios. After the TiSix contact layer is formed a barrier layer and a metal plug layer are formed thereover to form a contact structure. The method comprises forming a barrier layer 140 over the silicide contact layer 126; and forming a metal plug 160 over the TiN barrier layer 140. The metal plug 160 is composed of Al or W.

Abstract: A method and structure is described for a DRAM cell having a double wall tub shaped capacitor. The structure of the capacitor has two embodiments: a double wall tub shaped capacitor and a double wall cup shaped capacitor. In a first embodiment for the tub shaped capacitor, the method comprises using two masks to form a tub shaped hole partial through an insulating layer and a concentric contact hole over the source. A polysilicon layer is formed over the insulating layer. Oxide spacers are formed on the sidewalls of the tub shaped hole. The polysilicon layer is patterned to separate adjacent electrodes. Next, a polysilicon inner wall is formed on the spacer sidewalls. The oxide spacers are then removed. The dielectric and top electrode are formed next thus completing the double wall tub shaped capacitor. The second embodiment for forming the cup shaped capacitor comprises forming an insulating layer the substrate surface and forming a photoresist layer with an opening over a source region.

Abstract: The invention provides a method of fabricating corrosion free metal lines. The method involves forming a thin polymeric passivation layer 30 over the metal layer 20 immediately after the metal deposition and before any photolithographic or etching processes. The polymeric passivation layer 30 is formed using a F-containing gas plasma treatment. The passivation layer prevents corrosion of the metal layer before a metal etch. The passivation layer is preferably composed of a polymeric of C, O, and F and has a thickness in a range of between about 40 and 80 .ANG.. The passivation layer is formed using a F-containing plasma treatment at a power of between 225 and 275 W, a pressure between about 80 and 120 mtorr, a CHF.sub.3 flow between about 40 and 60 sccm and for a duration between about 10 to 30 seconds. Following this, the metal layer is patterned using photo and etch steps.

Abstract: The present invention provides a protective shield for a plasma etcher. The protective shield 40 protects the chamber wall 30 around the etch detect window from plasma etching and electrical arcing. The invention comprises a plasma etcher 10 has a wall 30 surrounding a chamber 14. The wall has an opening 16. The wall 30 having an inside face 30A and an outside face 30B. An opening edge 30C defines the opening 16. A window 24 covers over the opening 16 and over a portion of the outside face 30B of the wall. The protective shield 40 covers the opening edge 30C around the opening 16 and a portion of the inside face 30A of the wall 30 around the opening 16. The shield 40 is composed of an electrically insulating and plasma resistant material whereby the protective shield 40 prevents the chamber from arching and generating particles and extends the lifetime of the wall 30.

Abstract: The present invention provides a method of manufacturing a capacitor for a high density memory device. The capacitor has a bottom electrode 70 having cylindrical walls 54A more closely spaced than the minimum photolithography dimensions. The method begins by providing a first conductive layer 30 that contacts the substrate. A polyoxide layer 36A is used to form an opening over the first conductive layer 30 that defines a dielectric stud 50. An important feature is the polyoxide layer 36A makes the opening 38A smaller than the photolithographic limits. Cylindrical walls 54A are formed on the sidewalls of the dielectric stud 50. Subsequent etches are used to form the bottom electrode 54A, 30B (70). The electrode of the present invention is smaller than the conventional minimum photo ground rules and the method is cost effective and highly manufacturable.

Abstract: The present invention provides a method for forming a transistor having a stacked gate electrode structure with two gates; a lower floating gate and an upper control gate. The floating gate is formed of three polysilicon layers--undoped/doped/undoped polysilicon layers. A substrate is provided having a tunnel oxide layer 20. Then sequentially a first undoped, first doped, and second undoped polysilicon layers 22,24,26 are formed over the tunnel oxide layer thereby forming a lower floating gate layer 22, 24, 26. An intergate dielectric layer 28,30,32 is then formed over the second undoped polysilicon layer 26. Next, an upper control gate 36 and a cap oxide layer are formed over the intergate dielectric layer 28,30,32. The stacked two gate electrode structure is formed by patterning the above mentioned layers. Then spaced source and drain regions 44 are formed on opposite sides of the stacked gate structure thereby completing the transistor.

Abstract: The present invention provides method to erase flash EEPROMS devices using a positive sine waveform (Vs) and negative Vg that drives a cell in to snapback breakdown to remove trapped electron in the tunnel oxide and improve device performance. The snapback breakdown operation of one cell in the array lowers the tunnel oxide electric field for all cells in the array. The snapback breakdown generates a substrate current that reduces the electric field thereby reducing electron and hole trapping.

Abstract: The present invention provides two main embodiments of a method of manufacturing a high capacitance cylindrical capacitor for a DRAM. The capacitor of the invention has a high capacitance because of the addition area 48C under the upper cylinder 48A and the hemispherical grain (HSG) layer 49 72. The first embodiment of the invention forms a HSG layer 49 over the inside of the cylindrical electrode 48A. The second embodiment forms a HSG layer 72 over both the inside and outside of the cylindrical electrode 70A. The invention also features four preferred methods for forming the first and second openings 30 34 in the second insulating layer. The first and second preferred methods use two optical masks to define the openings 30 34. The third and fourth methods use one photoresist layer 100 with 3 different thickness areas and a three step etch to define the first and second openings 30 34.