Abstract: The present invention provides a method of forming a low contact resistance butt contact 44 between a doped region 30 and a conductive line 16B 18B. The method begins by providing an isolation region 11 on a substrate. A conductive structure 16B 18B comprised of a first polysilicon line 16B and a tungsten silicide layer 18B is formed over the isolation region 11. The substrate has a butt contact area 28 adjacent to the isolation region 11. An inter-poly oxide layer 24 is formed over the resulting surface. A butt contact photoresist layer 26 having an opening 26A exposing the butt contact area 28 and adjacent portions of the isolation region 11 is formed over the oxide layer 24. In an important step, the exposed portions of inter-poly oxide layer 24 and the underlying "high resistivity" tungsten silicide line 18B are etched thereby exposing portions of the first polysilicon layer 16B 16C.

Abstract: The present invention provides a method of manufacturing a high nitrogen (N) content oxynitride layer 34A 34B over field oxide regions. The oxynitride layer 34A 34B prevents subsequent etches from forming recesses in the field oxide regions 30 and planarizes the surface. The method begins by forming a field oxide region 30 an isolation area in the substrate 22. A high N content oxynitride protection layer 34A 34B (an etch barrier) is then formed surrounding (over and under) the field oxide layer 30. The high N content oxynitride protection layer 34A 34B is formed by heating (e.g., annealing) the substrate in a gas environment comprising ammonia. The high N content oxynitride layer is preferably formed by rapidly thermally annealing the substrate at temperature between about 825.degree. and 875 .degree. C. in an ammonia containing environment with a partial pressure of between about 0.5 and 1.2 kg/cm.sup.2 .

Abstract: The invention provides a method of manufacturing a cylindrical capacitor for a DRAM that has a pin shaped plug 42 that increases the photo alignment tolerances between a pin plug 42 and a cylindrical top crown 50A. The invention provides a capacitor structure with a pin shaped plug hole 40 (40A 40B) that has a wide upper hemispherical plug hole 40B and a narrower cylindrical lower plug hole 40A. There are two embodiments to forming the pin plug hole 40. In the first embodiment, (1) an isotropic etch forms the wide upper hemispherical plug hole 40B followed by, (2) an anisotropic etch forms the narrower cylindrical lower plug hole 40B. In the second embodiment, the first insulating layer 30 is composed of an upper layer 30B (with a fast wet etch rate) and a lower layer 30A (with a slow wet etch rate). Then the layer 30 is etched by a wet and a dry etch (in either order) to form the pin plug opening 30.

Abstract: The present invention provides a method for fabricating a multiple pillar shaped capacitor which has pillars of a smaller dimension than the resolution of the photolithography tool. The invention has two embodiments for forming the pillars and third embodiment for patterning a conductive layer into discrete bottom electrodes. The method begins by forming a conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller then that of the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.

Abstract: The present invention provides a method of manufacturing a capacitor having a two step ladder cross sectional shape. The method begins by forming a first conformal layer and a first insulation layer over a substrate. A contact hole is opened through the first conformal layer and the first insulation layer. A first conductive layer and a first masking layer are formed over the first insulation layer and in the contact opening. Then, the first masking layer and the first conductive layer are patterned to form a first ridge over at least portions of the source region. A first dielectric layer composed of silicon oxide is then formed over the first conductive layer. The first dielectric layer is anisotropically etched to form spacers on the sidewalls of the ridge. The first conducive layer and the first masking layer are anisotropically etched using the spacers as an etch mask thereby forming the storage electrode having a two step ladder cross sectional shape from the remaining first polysilicon layer.

Abstract: The present invention provides a method of to planarize a spin-on-glass layer overlying a HDP-CVD oxide layer using a six etchback process. The process comprises: forming a spin-on-glass layer 40 over a plasma chemical vapor deposition (HDP-CVD)oxide layer 30 over spaced raised portions 20 on a semiconductor structure. The spin-on-glass and the density plasma chemical vapor deposition (HDP-CVD) oxide layer 30 are then planarized using a six etch back process comprising: Step 2, (Etch High), a CF4 gas flow of between about 88 and 108 sccm, CHF.sub.3 flow between about 35 and 45 sccm, an argon flow of between about 40 and 60 sccm, at a pressure of between about 210 and 310 mtorr, at a power of between 650 and 950 watts; Step 3 (Etch Low) a CF4 gas flow of between about 10 and 20 sccm, CHF.sub.

Abstract: The present invention provides a method of manufacturing a cylindrical capacitor which begins by forming an insulating layer and a passivation layer composed of silicon nitride is over a substrate. A plug contact opening is formed through the passivation layer and the insulating layer. The insulating layer in the plug contact opening is selectively wet etched. The wet etching forms an overhanging portion of the passivation layer. A bottom plug is formed in the contact opening. A first dielectric layer having a cylindrical electrode opening is formed over passivation layer and the plug is exposed. A second polysilicon layer is formed over the first dielectric layer and in the cylindrical openings. A second dielectric layer is formed over the second polysilicon layer and in the cylindrical electrode opening. The second dielectric layer and the second polysilicon layer are planarized.

Abstract: A method for manufacturing a double walled cylindrical stacked capacitor for a DRAM using only one photo mask is provided. An insulating layer having a contact opening is formed over a transistor. A first conductive layer is then formed over the insulating layer. The first conductive layer is patterned forming a central spine over the contact opening and portions of the first conductive layer are left covering the insulation layer. Dielectric spacers are formed on the sidewall of the central spine. The remaining portions of the first conductive layer over the first insulating layer are removed and upper portions of the central spine are removed forming a conductive base. Inner and outer conductive walls are formed on the sidewalls of the dielectric spacers thereby forming a double walled bottom electrode. The dielectric spacers are removed. A capacitor dielectric layer and a top electrode are formed over the bottom electrode forming the capacitor.

Abstract: The present invention provides a method of fabricating passivation layers over closely spaced metal lines on a substrate. More particularly, the invention forms a three layer sandwich of passivation layers comprised of (1) a first thin plasma enhance silicon nitride (PE-SiN) layer; (2) a silicon oxide layer; and (3) a second silicon nitride layer. The method begins by forming closely spaced metal lines 20 over a substrate surface. A first silicon nitride layer 24 is formed using a low powered plasma enhanced chemical vapor deposition process, over the metal lines 20 and the substrate surface. A silicon oxide layer 28 is then formed over the first silicon nitride layer. A second nitride layer 32 is formed, using a plasma enhanced chemical vapor deposition process, over the silicon oxide layer 28. The method further includes forming an insulating layer 36 over the second nitride layer. The passivation layers of the invention is preferably formed over the top metal layer.

Abstract: An apparatus for producing thin film coatings and/or dopant levels on semiconductor wafers or other substrates with improved film growth uniformity (of thickness and composition) and/or dopant uniformity is provided. The apparatus is positioned in a furnace tube between the wafers and a gas inlet. The apparatus comprises a conical shaped baffle.

Abstract: The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool.

Abstract: The present invention provides a method of manufacturing of planarizing an insulating layer using a sized reversed interconnect mask and two polish stop layers. Spaced interconnections 14 are provided over the semiconductor substrate 10. An insulating layer 22 is formed over the interconnections 14 forming valleys 18 between the spaced interconnections 14. A first polish stop layer 26 is formed over the insulating layer 22. A dielectric layer 30 is formed over the first polish stop layer 26. A second polish stop layer 36 is formed over the dielectric layer 30. The top of the second polish stop layer 36 over the valley 23 is coplanar with the top of the first polish stop layer 26 over the interconnect 14. A reduced size, reverse interconnect mask 40 is formed over the second polish stop layer 36. The reduced size, reverse interconnect mask 40 covers portions of the valleys 23 between the spaced interconnections 14.

Abstract: The preset invention provides a method of manufacturing miniature interconnects and capacitors for semiconductor memory devices. The method uses a configuration of two sets of spacers to form self aligned source/bit line contacts and capacitor storage electrodes. First spacers are formed on the sidewalls of an interlevel dielectric layer. The first spacers define the source/bit line contacts holes. Later, the second spacers are formed the sidewalls of the bit lines. The second spacers define the capacitor storage electrodes. The self-aligning process, which uses the two set of spacers, allows a wide processing overlay window for contact etching to form the contact holes and permits small contact holes with high aspect ratios. The method reduces the masking steps by defining both the source and drain contacts in the same masking step.

Abstract: The present invention provides a method of fabricating a field oxide layer having a reduced bird's beak using a nitride foot 70 and a first field oxide region 80A as a N.sub.2 implant mask. The N.sub.2 implant suppresses oxide growth around the perimeter of the field oxide and reduces the bird's beak. A pad oxide layer 20 and a first nitride layer 30 are formed over a substrate. The first nitride layer is partially etched back forming a residual first nitride layer in the areas where the field oxide will be formed. A polysilicon spacer is formed on the sidewalls of the first nitride layer and over a portion of the residual first nitride layer. The residual first nitride layer 31 is etched using the spacer 60 as an etch mask forming a nitride foot 70. The substrate is thermally oxidized in the field oxide area using the first nitride layer and the foot 60 as an oxidation barrier forming a first field oxide layer 80A having a bird's beak 85.

Abstract: A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48.

Abstract: A method of forming a transistor having silicide contacts to the gate and source/drain regions. A semiconductor substrate is provided having spaced field oxide regions and active areas. On the active areas, a gate structure is formed having a gate oxide, gate, and gate insulating layer. In an important step, the gate 18 is laterally etched to remove a first width of the gate. A second dielectric layer 22 composed of oxide is deposited over the sidewalls of the gate, the gate 18 and the substrate 10. The second dielectric layer 22 is etched forming sidewall spacers 24 on the sidewalls of the gate 18, the gate insulating layer 20, and the gate oxide layer. The gate insulating layer 20 is then removed with a selective etch. A metal layer 30 is deposited over the resulting surface. The metal layer 30 is heat treated forming a gate silicide contact 36 on the gate 18 and source and drain silicide contacts 34 on the active areas.

Abstract: The present invention provides a method of manufacturing an interlevel dielectric layer (ILD) which has reduced precipitates after an etch back of the borophosphosilicate glass (BPSG) ILD layer. A dielectric layer containing boron and phosphorous is deposited on the substrate. A reflow process is performed on the dielectric layer at a temperature in a range of between about 800.degree. and 950.degree. C. The dielectric layer is etched back using a reactive ion etch. In an important step, a surface treatment is performed on the dielectric layer thorough a plasma treatment. A plasma source gas for the surface treatment is of a gas selected from the group consisting of Ar, NO.sub.2, N.sub.2, and O.sub.2, at a temperature in a range of between about 250.degree. and 400.degree. C. at a pressure in a range of between about 1 mtorr and 5 torr, at a RF power in a range of between about 300 and 400 watts, and for a time in a range of between about 15 and 80 seconds.

Abstract: An improved process and integrated-circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate and a NMOS electro static discharge circuit formed in a P well on the substrate. The improvement includes an electro static discharge NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped gate polysilicon electrode of the electro static discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.

Abstract: To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has n-plug doped regions in said c-well areas. A stress release oxide layer is grown over the substrate surface. A first nitride layer 27 is formed over the stress release oxide layer 26. A C-well mask 29having C-well mask openings 28A is formed over C-well areas 28 and openings are formed in the first nitride layer. Impurities are implanted through the opening forming collector-well regions. The c-well mask is then removed. A n-well photoresist mask having n-well mask openings 42A is formed over the first nitride layer and openings are etched in the first nitride layer over N-well areas 40. Ions impurities are implanted through the n-well nitride opening 42A forming n-well regions 44 in the n-well area in the substrate 10. The n-well mask 42 is then removed.

Abstract: Two embodiments of a method are described for fabricating a DRAM cell having a T or Y shaped capacitor connected to a MOS transistor with source and drain regions. In a first embodiment, the method comprises using two masks to form a cylindrical hole partial through the insulating layer and a concentric contact hole over the source. A first conductive layer is formed over the first insulating layer, at least completely filling the trench and filling the contact hole. In a key step, the first polysilicon layer is chemically mechanically polished thereby forming a T shaped storage electrode. Next, a capacitor dielectric layer and a top electrode are sequentially formed over at least the T shaped storage electrode. The second embodiment form the contact hole and trench as described above. A conformal first conductive layer is formed over the first insulating layer, filling the contact hole and covering the sidewalls and bottom of the trench, but not filling the trench.