Abstract: A method of removing a seed layer 30 from areas over an insulting layer 20 where metal lines and pads will not be formed so that electroplated metal 50 can be chemical-mechanical polished without metal residue problems 151 and dishing problems. A key step of the invention is the patterning of the seed layer 30 to remove areas 40 of seed layer 30 that are not near the trenches 24. The method is as follows. An insulating layer 20 is formed having a plurality of trenches 24. A seed layer 30 is formed over the insulating layer 24. The seed layer 30 is comprised of a trench seed layer 30B and a top seed layer 30A on the top surface of the first insulating layer. We pattern the top seed layer 30A by removing selected portions of the top seed layer 30A to form a seed layer "lip" 30C around the trenches 24 so that the remaining seed layer 30B 30C electrically connects the trench seed layers 30B in the plurality of trenches 24. Metal is plated on the trench seed layer 30B filling the trenches 24.

Abstract: The present invention provides a novel method for fabricating a buried contact extending under the first conductive layer 16 and subjacent first insulating layer 14. A first insulating layer 14 and a first conductive layer are formed over a silicon substrate 10 having isolation structures 12. A photoresist mask 18A having a buried contact opening 20 is formed over the first conductive layer. The first conductive layer 16 and the first insulating layer 14 are etched through the photoresist mask 18A. A width 21 of the photoresist mask 18A adjacent to the buried contact opening 20 is removed using a descum process, thereby forming an expanded opening 20A and an exposed ring 16A of the first conductive layer 16 with subjacent first insulating layer 14.

Abstract: The present invention provides a method of forming a contact structure comprised of: a silicon substrate, a titanium silicide layer, a barrier layer (i.e., TiN or TiNO), and a metal layer (e.g., Al or W). There are three embodiments of the invention for forming the titanium silicide layer and two embodiments for forming the barrier layer (TiN or TiNO). The first embodiment for forming a TiSix layer comprises three selective deposition steps with varying TiCl4: SiH4 ratios. After the TiSix contact layer is formed a barrier layer and a metal plug layer are formed thereover to form a contact structure. The method comprises forming a barrier layer 140 over the silicide contact layer 126; and forming a metal plug 160 over the TiN barrier layer 140. The metal plug 160 is composed of Al or W.

Abstract: A method of fabrication of a metal lines without dishing using damascene and chemical-mechanical polish processes. A Key feature is the hard cap layer that is only formed over the trench opening. The hard cap layer prevents dishing of the metal line and also allows faster CMP than blanket polish stop layers. The method includes forming a first dielectric layer having a first trench opening over a semiconductor structure. A metal layer is deposited in the first trench opening. The metal layer has a dimple. The metal layer is preferably composed of Al or Cu. A hard mask is formed having a first opening over the first trench opening. The first opening is at least partially over first trench opening. A hard cap layer (e.g., W or WSi.sub.x) is selectively deposited on the metal layer exposed in the first opening. The hard cap layer, the hard mask, and the metal layer are chemical-mechanical polished to completely remove the hard mask resulting in a metal line having a "dishing free" flat top surface.

Abstract: A method of patterning conductive lines using a bottom anti-reflective coating (BARC) composed of Poly-p-phenylene sulfide (PPS) film 30 formed using a Physical Vapor Deposition (PVD) process. The PPS BARC 30 is easy to remove and has superior planarization. The method comprises:a) forming conductive layer 26 over a semiconductor structure 10;b) forming a Poly-p-phenylene sulfide (PPS) layer 30 over said conductive layer using a Physical Vapor Deposition (PVD) process;c) forming a photoresist pattern 34 over said Poly-p-phenylene sulfide (PPS) layer 30; said Poly-p-phenylene sulfide (PPS) layer acting as a bottom Anti-reflective coating (BARC);d) etching said conductive layer 26 using said photoresist pattern 34 and as a mask forming a conductive pattern;e) removing said photoresist pattern 34;f) removing said Poly-p-phenylene sulfide (PPS) layer by heating and vaporizing said Poly-p-phenylene sulfide (PPS) layer.

Abstract: The present invention provides a method of manufacturing of planarizing an insulating layer using a reduced size reversed interconnect mask and an etch stop layer. Spaced interconnections 22 are provided over the semiconductor substrate 10. An etch stop layer 26 is formed over the raised portions 22. A dielectric layer 30 is formed over the etch stop layer 26. The top of the first dielectric layer 30 over the valley 23 is about coplanar with the top of the etch stop layer 26 over the raised portion 22. A reduced size, reverse interconnect (photoresist) mask 40 is formed over the first dielectric layer 30. The reduced size, reverse interconnect mask 40 covers portions of the valleys 23 between the raised portions. The first dielectric layer 30 is etched using the reverse interconnect mask 40 as an etch mask leaving dielectric blocks 30A over the narrow valleys 23. The dielectric blocks 30A fill in the valleys 23 between the raised portions thereby eliminating the need for a global planarization step.

Abstract: A method of planarizing a non-conformal oxide layer 40 forming shallow trench isolation between active areas 12 in a substrate. The invention uses a first chemical-mechanical polish (CMP) step to form openings 50 only over wide active areas. An etch is used to remove oxide 40 from only over the wide active areas 12A. A second CMP step is used to planarized the oxide layer 40. The invention begins by forming spaced trenches 30 in said substrate 10 defining active areas 12. A first insulating layer 40 composed of a non-conformal silicon oxide is formed by a HDPCVD process over the substrate and fills the trenches 30. A etch barrier layer 44 is formed over the first insulating layer 40. In a first chemical-mechanical polish (CMP) step, the conformal etch barrier layer 44 over only the wide raised portions 12A is polished to form a self-aligned first openings 50. The chemical-mechanical polishing of the conformal etch barrier layer forms a self-aligned etch mask.

Abstract: A structure of a readable alignment mark and method of manufacturing the readable alignment mark in an alignment mark area on a semiconductor substrate. A semiconductor substrate 10 comprising a product area 12 and an alignment mark area 30 is provided. The alignment mark area 30 has an outer area 40 and an inner area 50. The outer area surrounds 40 the inner area 50. A plurality of alignment mark trenches 24 is formed in the substrate 10 within the inner area 50. A pad oxide layer 20 and a silicon nitride layer 44 are formed sequentially in at least the alignment mark area 12. An isolation trench 43 is formed in the substrate 10 in at least the outer area 40. An insulating layer 46 is formed at least over the alignment mark area 30. The insulating layer 46 is chemical-mechanical polished thereby removing a first thickness of the insulating layer from the inner alignment mark area 50 and leaving a residual insulating layer 46A in the alignment mark trenches 48.

Abstract: The present invention provides a method of fabricating a tungsten (W) plug 36 contact to a substrate using a selective W CVD Process with a self-aligned W-Silicide Barrier layer 34. The method comprises the steps of: forming first insulating layer 20 over a silicon semiconductor substrate 10; forming a first (contact) opening 24 in the first insulating layer 20 exposing the surface of the substrate; selectively growing a thin first tungsten layer 30 over the exposed substrate surface; rapidly thermally annealing the substrate forming a thin first tungsten silicide layer 34 from the thin first tungsten layer 30; selectively depositing a tungsten plug 36 over the first thin tungsten silicide layer 34 substantially filling the first opening 36 thereby forming a W plug contact. The RTA/W silicide layer 34 lowers the contact resistance, increases the adhesion and facilitates the selective deposition of the W plug 36.

Abstract: A method of planarizing a non-conformal HPDCVD STI oxide isolation using an underlying first nitride layer and an overlying second nitride polish stop layer. The HPDCVD oxide is deposited so that the second nitride polish stop is formed coplanar with the first nitride layer over the center of narrow trenches. Both first and second nitride layers act as polish stops. The invention forms a first nitride layer over the substrate. Wide and narrow trenches are then etched in the substrate. In an important step, a non-conformal HDPCVD oxide layer is formed filling the trenches to a level about 500 .ANG. above the substrate surface. Then a second nitride layer is formed over the non-conformal HDPCVD oxide layer. Next, the structure is chemical-mechanical polished using both the first and nitride layers as polish stops. The second nitride layer and narrow extruded parts of the HDP-CVD oxide layer are removed in a DHF etch. Next, the first nitride layer is removed.

Abstract: Method and baths for electroless depositing Cu on a semiconductor chip using four preferred Cu electroless baths. All four preferred electroless baths use hypophosphite as a reducing agent. The 4 baths use the following mediators (1) Nickel sulfate, (2) Pd Sulfate (3) Co Sulfate (4) Fe Sulfite, and complexing agents (Na Citrite, Boric Acid, Ammonium Sulfite). The baths can operate at a pH between 8 and 10. The invention forms high purity Cu interconnects having adequate step coverage to form in a hole having an aspect ratio greater than 2.7 to 1.

Abstract: A method of manufacturing an insulating layer 30 (IMD layer) that has a uniform etch rate and forms improved via/contact opening profiles. The method forms a coating film 11 of silicon oxide over the chamber walls 22 of a CVD reactor. Next, the wafer 12 is loaded into the CVD reactor 20. A first insulating layer 30 composed of oxide preferably formed by a sub-atmospheric undoped silicon glass (SAUSG) using TEOS is formed over the semiconductor structure 12. Via/Contact Openings 32 are then etched in the insulating layer 30. The coating film 11 over the interior surfaces (e.g., reactor walls) 22 improves the etch rate uniformity of the first insulating layer 30. The first insulating layer 30 is preferably a inter metal dielectric (IMD) layer.

Abstract: The present invention provides a method of removing an shallow trench isolation (STI) oxide layer 38 from over alignment marks 30. The invention has two major features: (1) A STI photoresist mask 42A that is used to etch Alignment area trenches 34 around alignment marks 30 and to etch STI trenches 35 in device areas 14; and (2) A "reverse tone" STI photoresist mask 42B that is used to remove the isolation oxide 38 from over the alignment marks 30 and from over the active areas 37. The method begins by providing a substrate 10 having a device area 14, an alignment mark trench area 16; and an alignment mark area 18. A polish stop layer 20 22 is formed over the substrate 10. A trench isolation resist layer 42A is used to etch alignment area trenches 34 around the alignment marks 34 and STI trenches 35 in the device areas. A dielectric layer 38 is formed over the substrate.

Abstract: The present invention provides a method of inter-poly oxide (IPO) layer underlying a polysilicon resistor in a memory product. The IPO layer 15 is formed by a modified low pressure SACVD-O.sub.3 -TEOS process that gives the IPO layer a smoother surface and good planarization. This IPO layer gives the overlying polysilicon resistors a more uniform resistance. The method begins by providing a semiconductor structure 10. Next, in an important step, an inter-poly oxide (IPO) layer 11 is formed using low pressure ozone assisted sub-atmospheric chemical vapor deposition (SACVD O.sub.3 -TEOS) process at a pressure between about 20 and 150 torr. A polysilicon resistor 15 is then formed on said inter-poly oxide (IPO) layer. The memory device is completed by forming passivation and conductive layers thereover.

Abstract: A method of manufacturing a memory device having embedded logic. The memory and logic FETS have two different two gate oxide 20 34 thicknesses. The method integrates (1) a salicide contact process 72 74 (logic devices) and dual gate (N+/P+) logic gate 24A 24B technology with (2) memory device Polycide with Self aligned Contact 80 Technology.

Abstract: A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP--transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises:a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O.sub.

Abstract: A method for filling shallow trenches 28 with a HDPCVD oxide 50. The invention has two liners: (a) a thermal oxide liner 36 and (b) an overlying conformal O.sub.3 -TEOS protective liner 40. The O.sub.3 -TEOS protective liner 40 prevents the HDPCVD oxide 50 from sputter damaging the trench sidewalls and the masking layer 24. The O.sub.3 -TEOS layer has novel process temperature (400 to 560.degree. C.) and low pressure (40 to 80 torr) that allows the O.sub.3 -TEOS layer to deposit uniformly over thermal oxide liner 36. The method begins by forming pad oxide layer 20 and a barrier layer 24 over a substrate. A trench 28 is formed in the substrate 10 through the pad oxide layer 20 and the barrier layer 24. A thermal oxide liner 36 and a protective O.sub.3 -TEOS liner layer 40 are formed over the walls of the trench 28 and over the barrier layer 24. Lastly, a high density plasma chemical vapor deposition (HDPCVD) oxide layer 50 is formed over the protective liner layer 40 filling the trench 28.

Abstract: The present invention provides a method of forming closely spaced interconnections over a semiconductor structure using conventional photolithographic and etching methods and tools. The process which begins by providing an insulating layer 14 over a semiconductor structure 10. A conductive layer and an isolation layer are sequentially formed over the insulating layer 14. The conductive layer is patterned forming spaced first interconnects 16 covered by isolation layer blocks 20. Sidewall spacers are then formed on the sidewalls of the first interconnects and the isolation layer blocks 20. A second conductive layer is formed over the resulting surface. The second conductive layer is planarized forming second interconnects 30 and excess conductive pieces 31 between the sidewall spacers. The excess conductive pieces 31 are intended to be removed.

Abstract: A method of annealing an interlevel dielectric (IDL) layer 24 composed of PE-TEOS oxide before contact openings are formed in the ILD layer. The anneal prevents the contact openings 30 in IDL layer 24 from shifting and causing contact problems (contact oblique 33). The method begins by forming a first insulating layer 16 20 over a semiconductor structure 12. An ILD layer 24 composed of silicon oxide formed by a PECVD process using TEOS overlying the structure 12. In a key step, first rapid thermal anneal (RTA) is performed on the interlevel dielectric layer 24. The first RTA is preferably performed at a temperature in a range of between about 940 and 1100.degree. C. for a time in a range of between about 10 and 120 seconds. A contact hole 30 is then formed through the first insulating layer and the interlevel dielectric layer 24. The invention's first rapid thermal anneal prevents the ILD layer 24 from shrinking and shifting that distorts the contact hole 30.

Abstract: A method of forming a metal gate for a CMOS device using a replacement gate process wherein sidewall spacers are formed on a dummy electrode prior to forming the metal gate allowing source and drain formation prior to metal gate formation and a tungsten layer is selectively deposited to act as an each or CMP stop and to reduce source and drain resistance. The process begins by forming a dummy gate oxide layer and a polysilicon dummy gate electrode layer on a substrate structure and patterning them to form a dummy gate. Lightly doped source and drain regions are formed by ion implantation using the dummy gate as an implant mask. Spacers are formed on the sidewalls of the dummy gate. Source and drain regions are formed by implanting ions using,the dummy gate and spacers as an implant mask and performing a rapid thermal anneal. A tungsten layer is selectively deposited on the dummy gate electrode and the source and drain regions.