Abstract: The present invention provides a method of manufacturing a cylindrical capacitor which has plug spacers that reduce capacitor size and increase overlay tolerances. The method begins by forming an insulating layer and a passivation layer over a substrate. A plug opening is formed through the passivation layer and the insulating layer. A polysilicon plug is formed in the plug opening. Plug opening spacers are formed on the sidewalls of the insulating and passivation layers in the plug opening. A first dielectric layer having a bottom electrode opening is formed over passivation layer and the plug is exposed. A third polysilicon layer is formed over the first dielectric layer and on the sidewalls of the first dielectric layer. A second dielectric layer is formed over the third polysilicon layer and in the bottom electrode opening. The second dielectric layer and the third polysilicon layer are RIE etched down to the level on the top surface of the first dielectric layer.

Abstract: The structure and method is provided which prevents moisture and contamination from diffusing through openings (e.g., fuse windows) in insulating layers to product devices. Three moisture barrier layers form a moisture impervious boundary system to prevent moisture from diffusing from a fuse window into other overlying layers and into product devices. First and second barrier layers are formed insulation layers below the fuse. A third barrier layer is formed over an uppermost insulation layer, the sidewalls of a fuse window and over the fuse. The first and third barrier layers form a seal in the fuse area. The method comprises forming an insulating layer 52 54 over portions of said substrate 50 including in said fuse window area 63. A first barrier layer 56, a first interlevel dielectric layer 58 are formed over the insulating layer. A second barrier layer 60 is formed over said first interlevel dielectric layer 58.

Abstract: The guard ring is a barrier which prevents contaminates from diffusing through a window opening through insulating layers to adjacent semiconductor devices. The guard ring is formed surrounding a window in the insulation layers over a fuse link or an alignment mark. The guard ring is an annular metal ring that penetrates two or more insulating layers and contacts the substrate.

Abstract: The present invention provides a structure and a method of electrically connecting wiring layers by forming a stacked plug interconnect. The first wiring layer is formed over a dielectric layer and a top barrier layer is formed over the top of the first wire layer. Next, first sidewall spacers preferably composed of titanium nitride and tungsten are formed on the first wire layer sidewalls. An inter metal dielectric layer is formed over the surface. A via is then etched exposing the first wiring layer. The first titanium nitride/tungsten spacers act as an etch stop for the via etch and also increase the contact area of the wiring layers. A tungsten plug with an outer TiN barrier layer is formed filling the via contacting the first wiring layer. On top of the tungsten plug, a second wiring layer is formed also having titanium nitride and tungsten sidewall spacers. The spacers also fill in the recesses in the TiN plug barrier layer and fill in dimples in the top of the tungsten plugs.

Abstract: The invention provides a combination of a nozzle and a vacuum hood. The vacuum hood has a chamber that surrounds the tip of the nozzle and removes residue from the tip by a vacuum which flows in the chamber past the nozzle tip. This vacuum catches and removes residue from the nozzle tip and prevents the reside from interfering with the spraying action or dripping down. The method of the instant invention provides for dispensing a fluid from a nozzle without dripping fluid from the nozzle having a vacuum hood. The method comprises: (a) dispensing a fluid on a rotating semiconductor wafer through a nozzle over the wafer; (b) terminating the fluid flow through the nozzle; (c) creating an upward flow of gas about the dispensing nozzle when the flow of fluid through the nozzle is terminated; (d) capturing any fluid residue from the nozzle in the upward flow of gas; (e) removing the wafer and positioning another wafer; and (f) terminating the upward flow of gas; and repeating the process of steps (a) through (f).

Abstract: The present invention provides a method of manufacturing a stacked cylindrical capacitor having a smooth top cylindrical surface and uniform height. A first insulating layer 20 is formed over the substrate 10. A barrier layer 22 having an opening 23 is formed over a first insulating layer 20 on a substrate. A second insulating layer 24 composed of silicon oxide is formed on the barrier layer 22. The second insulating layer 24 and the first insulating layer 20 are patterned forming a first cylindrical opening 26 exposing the active region of the substrate 10 and forming a second cylindrical opening 30 in the second insulating layer 24 that exposes portions of the barrier layer 22. A conformal polysilicon layer 34 is formed over the resultant surface and the walls of the cylindrical openings 26 30. A planarizing layer 36 is formed over the resulting surface and then etched back forming a planarizing plug 36A that partially fills the second cylindrical opening 30A.

Abstract: A method of forming a transistor having silicide contacts to shallow gate, source and drain regions 18 in a substrate 10 is disclosed. The transistor has an extended sidewall spacer that covers an outer top portion of the gate. The extended sidewall spacers of the invention extend the distance (leakage path) between the gate and the source/drain thereby reducing the leakage current. The transistor is provided having a gate electrode 12,14,16 and spaced lightly doped source and drain regions 18. A key part of the invention is that the gate insulating layer 16 is laterally etched forming a gate cap insulating layer 16A which only covers an inner central portion of the gate 14. Next, a dielectric layer 20 is formed over the lightly doped source and drain regions 18 and the gate electrode 12,14,16A . The dielectric layer 20 is then anisotropically etched forming extended sidewall spacers 20A which cover the outer top portion of the gate 14.

Abstract: A mask chuck for fabricating a semiconductor mask which reduces spinning turbulence comprising: a top plate attached to a base by supports. The top plate has a cylindrical shape, a top surface, and rounded outer edges. The top plate preferably has a square opening extending through the top plate. Preferably four ledges extend out from along the corners of the opening. The four edges of the opening having four notches having ledges. Pins are mounted on the ledges. The pins extend upward towards the top surface of the top plate. A mask rests on the pins and the pins are adjusted so that the top surface of the mask is even with the top surface of said top plate. The mask chuck reduced turbulence having a cylindrical aerodynamic shape, an opening which is closely fitted to the mask and pins which level the top surface of the mask with the top surface of the chuck.

Abstract: The present invention provides a method of manufacturing a cylindrical capacitor for a DRAM. A resist layer is first used to pattern a first conductive layer and an oxidation barrier layer into a cylindrical bottom electrode. In a critical step, the resist layer is laterally etched removing a lateral portion of the resist layer thereby exposing an outer cylindrical section of the barrier layer. Using the now narrower (laterally plasma etched) resist layer as a mask, the exposed portions of the oxidation barrier layer are etched away. A masking layer is formed over the sidewalls and the exposed portions of the bottom electrode by an oxidation process. The oxidation barrier layer then is removed. The bottom electrode is anisotropically etched using the masking layer as a mask forming a cylindrical storage electrode. A dielectric layer and top plate electrode are formed over the storage electrode to form the capacitor.

Abstract: A method for backside grinding a semiconductor wafer and forming a contamination free bonding pad connection. The method comprises forming a passivation layer over a metal layer. Applying a photoresist pattern with an opening which will define a bonding pad area and removing the passivation layer exposed in the opening. Next, the photoresist is removed, but a polymer residue is often formed on the surfaces of the passivation layer surrounding the bonding pad. In a novel step, the residue is removed using an etchant containing Dimethylsulfoxide (D.M.D.O.) aud Monoethanolamine (M.E.A.) and is followed by au oxygen plasma treatment. Next, the device side of the wafer is covered with a protective tape and the backside of the wafer is grouud back. The tape is removed revealing a contamination free bonding pad area. A bonding connection is then made to the bonding pad.

Abstract: The present invention provides a method of manufacturing a sacrificial self aligned sub-atmospheric chemical vapor deposition (SACVD) O.sub.3 TEOS layer 50 70 over a trench oxide 40 to protect the trench oxide from excessive subsequent etch steps. The SACVD O.sub.3 TEOS layer has a higher deposition rate over the trench oxide layer 40 than over the surrounding non-trench thermally grown pad oxides. The trench oxide is preferably formed using a process of PECVD, LPTEOS, or O.sub.3 -TEOS. The invention provides two preferred embodiments: (1) a first self aligned sacrificial O.sub.3 TEOS oxide layer 50 deposited before the pad oxide etch and (2) a second self aligned sacrificial O.sub.3 TEOS oxide layer 70 deposited before the sacrificial implant oxide etch. The invention can be applied in a variety of situations where the trench oxide is exposed to damaging etches.

Abstract: An integrated circuit includes a conductive fusible link that may be blown by heating with laser irradiation, The integrate circuit comprises a silicon substrate; a first insulating layer; a fusible link on the first layer; a second insulating layer overlying the first layer and the fusible link; an opening through the second layer exposing the fuse; and a protective layer over the surfaces of the opening. A laser beam is irradiated through the opening and the protective layer to melt the fusible link. The protective layer is highly transparent to a laser beam and does not interfere with the laser melting (trimming) operation.

Abstract: An improved structure and a process for forming an interlevel dielectric layer having a low capacitance between closely spaced metallurgy lines is provided. The method begins with a substrate surface having closely spaced metallurgy lines. A silicon oxide dielectric layer having a closed void between adjacent metallurgy lines is formed using electro cyclotron resonance techniques. The voids in the silicon dioxide dielectric layer are formed by controlling the ECR process parameters to achieve a proper etch to deposition ratio. The etch to deposition ratio of the silicon oxide layer is adjusted to the particular height and spacing between the metallurgy lines. Next, a spin-on-glass layer is formed over the silicon oxide dielectric layer. Portions of the SOG layer are etched back or chemically mechanically polished. The void (air) has a lower capacitance than the ECR silicon oxide layer.

Abstract: A high capacitance stacked capacitor is defined using one optical mask for two masking steps where one masking step includes overexposing the resist layer. The method begins by forming a planarizing layer 28 over the substrate surface. A first photolithographic process using a first optical mask is used to form a first opening in the planarizing layer 28. A polysilicon stud 38 is formed in the first opening. A dielectric layer 40 is formed over the planarizing layer 28. A second opening 44 is formed in the dielectric layer 40 using a second photolithographic process using the same first optical mask. The second photoresist layer is exposed at a higher energy than the exposure of the first photoresist layer. The dielectric layer 40 is etched using the second photoresist pattern as an etch mask and forming the second opening 44 in the dielectric layer 40. Because of the overexposure, the second opening 44 has a larger open dimension than the first opening 36.

Abstract: A sample holder tripod for grinding a square edge on a sample and for observing the sample with a microscope is provided. The sample tripod comprises: a tripod base, a support, two adjustable micrometer leg assemblies, a sample stage and a grinding bubble indicator. The micrometer leg assembles are mounted to the tripod through a micrometer mounting holes. The stage has a means to mount a sample. The sample holder tripod can be positioned to view the sample in a top down view and cross-sectional view without having to re-focus the microscope.

Abstract: The present invention provides method to erase and program flash EEPROMS devices using a clipped sine waveform (Vg). The clipped sine waveform reduces the tunneling oxide electric field between the floating gate and the source or drain region thereby reducing electron trapping. The method for the erase cycle comprises: applying a positive voltage to a source region; grounding a well region; floating the drain region; and simultaneously applying a negative clipped sine waveform voltage to a control gate during the erase cycle. The program cycle of the invention comprises: applying a voltage to a drain region; grounding a well region; floating a source region; and simultaneously applying a clipped sine waveform voltage to the control gate whereby the clipped sine waveforms reduce the electric field in a tunnel oxide layer which reduces the electron trapping.

Abstract: The invention is a process for filling narrow isolation trenches with thermal oxide using a nitride spacer and a second trench etch. The method begins by providing forming a pad oxide layer 20 and a first nitride layer 30 over a substrate. A first opening is formed in the pad oxide layer 20 and first nitride layer 30. The substrate is then etched through the first opening forming a first trench 40 in the substrate. A thin oxide film 50 is then grown over the substrate in the bottom and sidewalls of the first trench 40. Nitride spacers 60 are grown over the sidewalls of the first trench and over the thin oxide layer 40 on the sidewalls of the trench. A portion of the thin oxide film 50 on the bottom of the trench is etched. The substrate in the bottom of the first trench is etched forming a second trench 70. The etch exposes portions of the substrate on the bottom of the deeper second trench.

Abstract: An improved method and apparatus for applying a primer to a wafer surface prior to coating the wafer with photoresist is provided. The method comprises priming a wafer with HMDS, removing the wafer from the priming chamber, and closing the chamber. Next, the chamber, piping and primer source are evacuated. The bubbler canister, piping and wafer chamber are held at a pressure of about 15 inches H.sub.2 O while the priming tool is idle between wafer priming operations. By maintaining the vaporizer, piping and wafer chamber at a partial vacuum, the primer will be prevented from condensing and forming harmful droplets on the wafer surface. The invention prevents primer condensation from forming on the wafer, thus improving photolithographic yields and device yields.

Abstract: The present invention provides a structure and method of manufacturing an interlevel/intermetal dielectric layer for a semiconductor device. The method begins by forming a stepped pattern 16 on a semiconductor structure 12. A barrier layer 20 composed of silicon oxide is formed on the semiconductor substrate so as to cover the surface of the stepped pattern 16. A first insulating layer 22 composed of silicon oxide is then formed over the barrier layer 20. A high P (phosphorous) content silicon glass layer 24 preferably is formed over the first insulating layer 22. The high P content silicon glass layer 24 has a phosphorous concentration in a range of about 4 and 10 weight percent. Next, in an important step, a graded P content silicon glass layer 26 is formed over the high P content silicon glass layer 24. The graded P content silicon glass layer 26 has a phosphorous concentration in a range of about 0.1 and 4 weight percent.

Abstract: The structure and method is provided which prevents moisture and contamination from diffusing through openings (e.g., fuse windows) in insulating layers to product devices. Three moisture barrier layers form a moisture impervious boundary system to prevent moisture from diffusing from a fuse window into other overlying layers and into product devices. First and second barrier layers are formed insulation layers below the fuse. A third barrier layer is formed over an uppermost insulation layer, the sidewalls of a fuse window and over the fuse. The first and third barrier layers form a seal in the fuse area. The method comprises forming an insulating layer 52 54 over portions of said substrate 50 including in said fuse window area 63. A first barrier layer 56, a first interlevel dielectric layer 58 are formed over the insulating layer. A second barrier layer 60 is formed over said first interlevel dielectric layer 58.