Patents Represented by Attorney William Park & Associates Ltd.
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Patent number: 8319264Abstract: A semiconductor device comprises: a semiconductor substrate including an active region defined as a device isolation film; a bit line contact hole obtained by etching the semiconductor substrate; a bit line contact plug having a smaller width than that of the bit line contact hole; and a bit line connected to the upper portion of the bit line contact plug, thereby preventing a short of the bit line contact plug and the storage node contact plug to improve characteristics of the semiconductor device.Type: GrantFiled: December 28, 2010Date of Patent: November 27, 2012Assignee: SK Hynix Inc.Inventor: Seung Bum Kim
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Patent number: 8319544Abstract: A mode determination apparatus in a semiconductor apparatus includes a first condition detection block configured to generate a first condition signal in response to a clock enable signal activated when the semiconductor apparatus enters a dynamic voltage scaling mode, a second condition detection block configured to generate a second condition signal in response to an external high voltage in the dynamic voltage scaling mode, the external high voltage having a voltage level in the dynamic voltage scaling mode different from a voltage level in a normal mode, and a signal processing block configured to generate a dynamic voltage scaling mode signal in response to the first condition signal and the second condition signal.Type: GrantFiled: November 16, 2010Date of Patent: November 27, 2012Assignee: SK Hynix Inc.Inventor: Young Do Hur
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Patent number: 8319327Abstract: A semiconductor package includes at least two semiconductor chips stacked to have step surfaces and possessing bonding pads disposed over the step surfaces. Conductive patterns are disposed over the step surfaces and electrically connect the bonding pads of the semiconductor chips with one another. An insulation member is formed over side and upper surfaces of the stacked semiconductor chips excluding the step surfaces and the conductive patterns.Type: GrantFiled: January 25, 2011Date of Patent: November 27, 2012Assignee: SK Hynix Inc.Inventor: Min Suk Suh
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Patent number: 8315113Abstract: Disclosed is a non-volatile semiconductor memory circuit with an improved resistance spread characteristic distinguishing set data and reset data. The non-volatile semiconductor memory circuit includes a memory cell array, and a read/write circuit block configured to differentiate the current drivability based on the mode of operation, wherein the current drivability is provided in response to a bias signal based on set or reset state of data.Type: GrantFiled: January 28, 2010Date of Patent: November 20, 2012Assignee: SK Hynix Inc.Inventor: Hyuck Soo Yoon
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Patent number: 8315089Abstract: A phase change memory device having an improved performance that minimizes cell degradation is presented. The phase change memory device includes: a cell array, a sense amplifier, a write driving unit, and a reference level selecting unit. The cell array has a phase change resistor is configured to read/write data. The sense amplifier is configured to compare a reference voltage with a sensing voltage received from the cell array. The write driving unit is configured to supply a driving voltage corresponding to write data to the cell array. The reference level selecting unit is configured to select a read reference voltage in a read mode so as to output the reference voltage, and to select a reference voltage corresponding to input data in a write verifying mode so as to output the reference voltage.Type: GrantFiled: June 22, 2011Date of Patent: November 20, 2012Assignee: SK Hynix Inc.Inventors: Hee Bok Kang, Suk Kyoung Hong
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Patent number: 8315116Abstract: A repair circuit of a semiconductor memory apparatus includes a repair address detection circuit that determines the occurrence of a failure in a memory block based on a plurality of test data signals outputted from the memory block, and stores an address corresponding to the memory block determined to have failed as a repair address, and an anti-fuse circuit that receives the repair address from the repair address detection circuit and electrically programs the repair address to store a programmed address.Type: GrantFiled: July 20, 2010Date of Patent: November 20, 2012Assignee: SK Hynix Inc.Inventors: Je Yoon Kim, Ki Chang Kwean
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Patent number: 8310045Abstract: A semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface, a heat dissipation member, defined with a cavity, disposed on the first surface of the first semiconductor chip and having a plurality of metal pillars which contact the first semiconductor chip, and one or more second semiconductor chips stacked on the first surface of the first semiconductor chip in the cavity to be electrically connected with one another and with the first semiconductor chip.Type: GrantFiled: January 25, 2011Date of Patent: November 13, 2012Assignee: SK Hynix Inc.Inventor: Ho Young Son
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Patent number: 8305823Abstract: A semiconductor integrated circuit having a sense amplifier includes first and second inverters each having an output terminal coupled to an input terminal of the other inverter. The first inverter is configured to be activated in response to a first and a third activation signals, and the second inverter is configured to be activated in response to a second and a fourth activation signals. The first and third activation signals and the second and fourth activation signals are provided through separate signal sources from each other.Type: GrantFiled: December 29, 2009Date of Patent: November 6, 2012Assignee: SK Hynix Inc.Inventors: Myoung Jin Lee, Hyung Sik Won
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Patent number: 8300460Abstract: A nonvolatile memory device comprises a page buffer unit comprising page buffers, each coupling first and second input and output (IO) lines and a latch circuit for outputting data together or coupling a sense node and the first or second I/O line together, in response to an operation mode; a Y decoder unit comprising decoders, each selecting one or more of the page buffers in response to address signals and outputting a first or second control signal to the selected page buffers in response to the operation mode; a mode selection unit outputting first and second operation selection signals for selecting the operation mode; and an I/O control unit comprising I/O control circuits, each detecting data, inputted and output through the first and second I/O lines, and outputting the detected data or coupling one of the first and second I/O lines to a data line.Type: GrantFiled: June 29, 2010Date of Patent: October 30, 2012Assignee: SK hynix Inc.Inventor: Ho Youb Cho
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Patent number: 8300495Abstract: A block control command generation circuit includes first and second latch units, an input selection unit, a pull-down driving unit, and an output selection unit. The first and second latch units store initial values at different levels in response to initialization signals. The input selection unit selectively transmits a first block control signal to the first latch unit in response to an input enable signal. The pull-down driving unit selectively pull-down drives an input node of the second latch unit in response to a second block control signal and the input enable signal. The output selection unit outputs signals, which are stored in the first and second latch units, as first and second block control command signals in response to an output enable signal, respectively.Type: GrantFiled: December 31, 2010Date of Patent: October 30, 2012Assignee: SK Hynix Inc.Inventors: Jung Mi Tak, Hyuck Soo Yoon, Ji Hyae Bae
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Patent number: 8300485Abstract: A sense amplifier is configured to transfer data on a first data I/O line to a second data I/O line or to transfer data on the second data I/O line to the first data I/O line. The first data I/O line is substantially continuously coupled to the second data I/O line during an active operation.Type: GrantFiled: December 7, 2010Date of Patent: October 30, 2012Assignee: SK Hynix Inc.Inventors: Kyu Nam Lim, Hong Sok Choi, Ki Myung Kyung, Mun Phil Park, Sun Hwa Park
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Patent number: 8298956Abstract: A method for fabricating a fine pattern includes forming a first photomask including first light transmission regions set in a line shape over a first phase shift mask (PSM) region and a first binary mask (BM) region adjacent to the first phase shift mask region. A second photomask may be formed to include second light transmission regions set in a line shape over a second phase shift mask region and a second binary mask region adjacent to the second phase shift mask region, wherein the second light transmission regions intersect the first light transmission regions. A resist layer may first be exposed using the first photomask and secondly exposed using the second photomask. The first and secondly exposed resist layer may be developed to form resist patterns with open regions corresponding to portions where the first light transmission regions intersect the second light transmission regions.Type: GrantFiled: September 23, 2011Date of Patent: October 30, 2012Assignee: SK Hynix Inc.Inventor: Hyun Jo Yang
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Patent number: 8300496Abstract: A semiconductor memory apparatus includes a clock control unit configured to receive a first clock when an enable signal is activated and generate a second clock which has a cycle closer in length to a target clock cycle than the first clock; a DLL input clock generation unit configured to output one of the first clock and the second clock as a DLL input clock according to a DLL select signal; and an address/command input clock generation unit configured to output one of the first clock and the second clock as an AC input clock according to the enable signal.Type: GrantFiled: November 18, 2010Date of Patent: October 30, 2012Assignee: SK Hynix Inc.Inventors: Tae Sik Yun, Hyung Dong Lee, Jun Gi Choi, Sang Jin Byeon, Sang Hoon Shin
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Patent number: 8295103Abstract: A nonvolatile semiconductor memory apparatus includes a control unit configured to generate a select signal and a driving control signal in response to a first enable signal and a second enable signal; a level shifting unit configured to enable a first shifting signal or a second shifting signal to a level of a pumping voltage in response to the select signal and the driving control signal; a first switching unit configured to apply a program voltage to a word line when the first shifting signal is enabled to the level of the pumping voltage; and a second switching unit configured to apply a pass voltage to the word line when the second shifting signal is enabled to the level of the pumping voltage.Type: GrantFiled: November 18, 2010Date of Patent: October 23, 2012Assignee: SK Hynix Inc.Inventor: Moon Soo Sung
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Patent number: 8289769Abstract: A nonvolatile memory device has memory cells coupled to bit lines and word lines and page buffers each coupled to one or more of the bit lines. Program and verification operations are performed on a first logical page from among first and second logical pages included in memory cells selected for a program operation. Data are loaded which will be programmed into the second logical page into first to third latches of a selected page buffer, coupled to the selected memory cells, from among the page buffers. A data setting operation is performed. The second logical page is programmed so that a distribution of threshold voltages of the selected memory cells has one of first to fourth threshold voltage distributions according to states of the data of the first to third latches and performing verification operations for the first to fourth threshold voltage distributions.Type: GrantFiled: June 29, 2010Date of Patent: October 16, 2012Assignee: SK Hynix Inc.Inventor: Sang Oh Lim
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Patent number: 8283971Abstract: An internal voltage generation circuit includes a voltage detection unit configured to generate a voltage detection signal that indicates whether a voltage level of an internal voltage is a first target voltage level or a second target voltage level higher than the first target voltage level, according to control of a normal operation signal. The internal voltage generation circuit also includes an operation control signal generation unit configured to selectively activate an operation control signal in response to the normal operation signal and the voltage detection signal, a periodic pulse signal generation unit configured to generate a periodic pulse signal in response to the operation control signal and the normal operation signal, and a charge pumping unit configured to generate an internal voltage by performing a charge pumping operation according to control of the periodic pulse signal.Type: GrantFiled: December 31, 2010Date of Patent: October 9, 2012Assignee: SK Hynix Inc.Inventor: Yoon Jae Shin
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Patent number: 8278967Abstract: A data driving impedance auto-calibration circuit includes: a detection block configured to calibrate a characteristic voltage generated by detecting an operation characteristic variation of an element, according to a code signal, and generate a calibrated characteristic voltage; a comparison block configured to compare the calibrated characteristic voltage with a reference voltage and output a comparison result signal; and a code calibration block configured to calibrate the code signal according to the comparison result signal.Type: GrantFiled: July 27, 2010Date of Patent: October 2, 2012Assignee: SK Hynix Inc.Inventor: Won Kyung Chung
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Patent number: 8278985Abstract: A synchronization circuit includes a first loop circuit configured to set an initial delay time by using first initial delay information and generate a first delay signal by changing a delay time of a first input signal, a second loop circuit configured to set the initial delay time by using second initial delay information and generate a second delay signal by changing a delay time of a second input signal, a duty cycle correction unit configured to correct a duty cycle of the first delay signal by using the second delay signal, and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to an internal delay signal of the first loop circuit and the first input signal.Type: GrantFiled: December 31, 2010Date of Patent: October 2, 2012Assignee: SK Hynix Inc.Inventor: Dong Suk Shin
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Patent number: 8279702Abstract: A semiconductor apparatus includes an individual-chip-designating-code setting block configured to generate a plurality of sets of individual-chip-designating-codes which have different code values or in which at least two sets of individual-chip-designating-codes have the same code value, in response to a plurality of chip fuse signals; a control block configured to generate a plurality of enable control signals in response to the plurality of chip fuse signals and most significant bits of the plurality of sets of individual-chip-designating-codes; and an individual chip activation block configured to compare individual-chip-designating-codes of the plurality of sets of individual-chip-designating-codes excluding the most significant bits, with chip selection addresses in response to the plurality of enable control signals, and enable one of a plurality of individual-chip-activation-signals depending upon a comparison result.Type: GrantFiled: July 21, 2010Date of Patent: October 2, 2012Assignee: SK Hynix Inc.Inventors: Jae Bum Ko, Sang Jin Byeon
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Patent number: 8279651Abstract: A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.Type: GrantFiled: June 29, 2010Date of Patent: October 2, 2012Assignee: SK Hynix Inc.Inventor: Jin Yong Seong