Abstract: Disclosed is an impulsive type liquid crystal driving device which inserts black data during a vertical blanking interval and then realizes motion picture, comprising: a liquid crystal panel for including a plurality of gate bus lines, which are arranged in one-direction, and a plurality of data bus lines which are arranged in a direction perpendicular to the plurality of gate bus lines; a gate driver section for sequentially scanning the plurality of gate bus lines during an active address interval in response to a second vertical starting signal, a vertical clock signal and an output enable signal, and scanning the plurality of gate bus lines during a vertical blanking interval in a unit of a predetermined number of lines; and a current boosting section for increasing current amount supplied to the gate bus lines during the vertical blanking interval in response to a pulse width modulation signal.

Abstract: A solid state mass storage device having a first storage area portion and a second storage area portion. The mass storage device including accessing means adapted to cause data to be stored in the first storage area portion in one of: only in memory cells belonging to columns of a first collection or only to columns of a second collection such that memory cells of the first storage area portion belonging to the first or second collection are left unprogrammed; or only in memory cells of even rows or only memory cells of odd row such that the memory cells of the first storage area belonging to the even or to the odd rows are left unprogrammed; or only in memory cells such that memory cells that are immediately adjacent to said memory cells in said row and column are left unprogrammed.

Abstract: A redundancy circuit of a semiconductor memory apparatus includes an enable signal generation unit configured to have a plurality of enable fuses corresponding to a first mat grouping information signal and a second mat grouping information signal and enable an enable signal when at least one of the plurality of enable fuses is cut and a mat grouping information signal corresponding to the cut fuse is inputted; a fail address setting control block configured to select the first mat grouping information signal or the second mat grouping information signal depending upon whether an enable fuse corresponding to the first mat grouping information signal is cut or not, and generate fail setting addresses; and a comparison section configured to compare the fail setting addresses with real addresses and generate a redundancy address.

Abstract: A flag signal generation circuit includes a first periodic signal detection unit, a second periodic signal detection unit, and a flag signal output unit. The first periodic signal detection unit is configured to detect a change in a level of a first periodic signal and generate a first detection signal. The second periodic signal detection unit is configured to detect a change in a level of a second periodic signal and generate a second detection signal. The flag signal output unit is configured to generate a pre-flag signal from the first and second detection signals, buffer the pre-flag signal in response to a mode register read signal, and output the buffered pre-flag signal as a flag signal.

Abstract: A circuit for controlling precharge in a semiconductor memory apparatus includes a read clock driver configured to drive an internal clock signal and generate a read burst clock signal; a read precharge control unit configured to generate a read auto precharge signal in response to the read burst clock signal, a burst end signal, and a read write mode signal; a write clock driver configured to drive the internal clock signal and generate a write burst clock signal in response to the read write mode signal and a data input off signal; a write precharge control unit configured to generate a write auto precharge signal in response to the write burst clock signal, the burst end signal, a write latency signal, and a write address combination signal; and a precharge signal generation unit configured to combine the read and write auto precharge signals and generate an auto precharge signal.