Patents Represented by Attorney Williams, Morgan and Amerson

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  • System and method for controlling an electrochemical etch process
    Patent number: 7993936
    Abstract: By evaluating a status signal on the basis of a fault detection classification mechanism in an electrochemical etch tool, a corresponding failure status of the tool may be obtained for each single substrate, thereby significantly reducing the risk of significant yield loss compared to conventional strategies. The fault detection and classification mechanism may be advantageously applied to the electrochemical removal of underbump metallization layers during the formation of solder bump structures.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kerstin Siury, Niels Rackwitz, Joern Schnapke, Frank Kuechenmeister
  • Assigning tasks in a distributed system
    Patent number: 7996458
    Abstract: A method and apparatus are provided for assigning tasks in a distributed system. The method comprises indicating to one or more remote systems in the distributed system that a task is available for processing based on a list identifying the one or more remote systems. The method further comprises receiving at least one response from the one or more remote systems capable of performing the task based on the indication. The method comprises allowing at least one of the remote systems to perform the task based on the at least one received response.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: August 9, 2011
    Assignee: Apple Inc.
    Inventors: Robert David Nielsen, Robert D. Willhoite, David Kramer
  • Vagus nerve stimulation by electrical signals for controlling cerebellar tremor
    Patent number: 7996088
    Abstract: A neurostimulator system for alleviating cerebellar tremor associated with multiple sclerosis, for instance, comprises a programmable electrical pulse generator. The programmable electrical pulse generator is programmed to generate electrical signals with the following parameters: a current magnitude of about 1 mA or less, a stimulation signal on-time to signal off-time ratio in the range of 2:1 to 1:1.8, signal on-times and off-times in the range of about 10 seconds to about 5 minutes, a signal frequency below 15 Hz, and a pulse width within the range of 50 ?s to 300 ?s. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: August 9, 2011
    Assignee: Cyberonics, Inc.
    Inventors: Francesco Marrosu, Maria Giovanna Marrosu
  • Enhanced stress transfer in an interlayer dielectric by using an additional stress layer above a dual stress liner in a semiconductor device
    Patent number: 7994059
    Abstract: By forming an additional stressed dielectric material after patterning dielectric liners of different intrinsic stress, a significant increase of performance in transistors may be obtained while substantially not contributing to patterning non-uniformities during the formation of respective contact openings in highly scaled semiconductor devices. The additional dielectric layer may be provided with any type of intrinsic stress, irrespective of the previously selected patterning sequence.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Martin Gerhardt, Martin Mazur, Joerg Hohage
  • Christmas tree with internally positioned flowmeter
    Patent number: 7992434
    Abstract: A measurement device is disclosed which includes a structure adapted to be removably coupled to a Christmas tree, a sleeve operatively coupled to the structure and a flowmeter positioned at least partially within the sleeve.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: August 9, 2011
    Assignee: FMC Technologies, Inc.
    Inventors: David Zollo, Andrew Beck, Sean Walters
  • Stress transfer by sequentially providing a highly stressed etch stop material and an interlayer dielectric in a contact layer stack of a semiconductor device
    Patent number: 7994072
    Abstract: By forming two or more individual dielectric layers of high intrinsic stress levels with intermediate interlayer dielectric material, the limitations of respective deposition techniques, such as plasma enhanced chemical vapor deposition, may be respected while nevertheless providing an increased amount of stressed material above a transistor element, even for highly scaled semiconductor devices.
    Type: Grant
    Filed: April 24, 2008
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joerg Hohage, Michael Finken, Ralf Richter
  • Input response override for an implantable medical device
    Patent number: 7996079
    Abstract: A method and apparatus for providing an override of an operational mode of an implantable medical device. An override input to enter an override mode is received. A determination as to whether a magnetic input has been received is made. A predetermined response to the magnetic input is blocked in response to receiving the override input.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: August 9, 2011
    Assignee: Cyberonics, Inc.
    Inventor: Randolph K. Armstrong
  • Gate dielectrics of different thickness in PMOS and NMOS transistors
    Patent number: 7994037
    Abstract: By providing a gate dielectric material of increased thickness for P-channel transistors compared to N-channel transistors, degradation mechanisms, such as negative bias threshold voltage instability, hot carrier injection and the like, may be reduced. Due to the enhanced reliability of the P-channel transistors, overall production yield for a specified quality category may be increased, due to the possibility of selecting narrower guard bands for the semiconductor device under consideration.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 9, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Martin Trentzsch, Karsten Wieczorek, Edward Ehrichs
  • Method of dynamic overhead channel power allocation
    Patent number: 7991421
    Abstract: The present invention provides a method for implementation in a base station that supports at least one downlink traffic channel and at least one overhead channel. The method includes determining power allocation(s) for overhead channel(s) based upon a measurement of downlink traffic channel power and a maximum transmission power of the base station. The method also includes transmitting signals over the overhead channel(s) using the power allocation concurrently with transmission of signals over the downlink traffic channel.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: August 2, 2011
    Assignee: Alcatel-Lucent USA Inc.
    Inventors: Asif Dawoodi Gandhi, Joseph Montalto
  • Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics
    Patent number: 7989352
    Abstract: By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.
    Type: Grant
    Filed: April 4, 2007
    Date of Patent: August 2, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
  • Estimating yield fluctuation for back-end planning
    Patent number: 7987013
    Abstract: A method for production planning includes receiving a first order quantity of a first device. A first yield estimate of the first device from a production line is determined. The first yield estimate is adjusted based on a first confidence factor associated with the first order quantity. A dispatch quantity for processing in the production line is determined based on the first order quantity and the adjusted first yield estimate.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: July 26, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Peng Qu
  • Method for forming a metal silicide having a lower potential for containing material defects
    Patent number: 7985668
    Abstract: Generally, the present disclosure is directed to a method of removing “weakened” areas of a metal silicide layer during silicide layer formation, thereby reducing the likelihood that material defects might occur during subsequent device manufacturing. One illustrative embodiment includes depositing a first layer of a refractory metal on a surface of a silicon-containing material, and performing first and second heating processes. The method further comprises performing a cleaning process, depositing a second layer of the refractory metal above the silicon-containing material, and performing a third heating process.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: July 26, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Ralf Richter, Torsten Huisinga, Jens Heinrich
  • Technique for electrochemically depositing an alloy having a chemical order
    Patent number: 7985329
    Abstract: By providing two or more consumable electrodes within a single reactor vessel, an alloy having a high degree of chemical ordering may be deposited in situ in that the current flows of the individual consumable electrodes are controlled to obtain a substantially layered deposition of the two or more metals. Hence, especially in copper-based metallization layers, the advantage of enhanced resistance against electromigration offered by alloys may be achieved without unduly reducing the overall conductivity.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: July 26, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Gerd Marxsen
  • Method of reducing erosion of a metal cap layer during via patterning in semiconductor devices
    Patent number: 7986040
    Abstract: During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: July 26, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christin Bartsch, Daniel Fischer, Matthias Schaller
  • Method of forming a metal directly on a conductive barrier layer by electrochemical deposition using an oxygen-depleted ambient
    Patent number: 7981793
    Abstract: By suppressing the presence of free oxygen during a cleaning process and a subsequent electrochemical deposition of a seed layer, the quality of a corresponding interface between the barrier material and the seed layer may be enhanced, thereby also improving performance and the characteristics of the finally obtained metal region. Thus, by identifying free oxygen as a main source for negatively affecting the characteristics of metals during a “direct on barrier” plating process, efficient strategies have been developed and are disclosed herein to provide a reliable technique for volume production of sophisticated semiconductor devices.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: July 19, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Preusse, Charlotte Emnet, Susanne Wehner
  • Semiconductor device including stress relaxation gaps for enhancing chip package interaction stability
    Patent number: 7982313
    Abstract: By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: July 19, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael Grillberger, Matthias Lehr
  • Shale shaker screens with aligned wires
    Patent number: 7980392
    Abstract: A screen for a vibratory separator, the screen including at least two layers of screening material, including a first layer and a second layer, the first layer made of a plurality of intersecting first wires, the second layer made of a plurality of intersecting second wires, the first wires including first shute wires and first warp wires, the second wires including second shute wires and second warp wires, certain of the first warp wires aligned with a second warp wire, and/or certain of the first shute wires aligned with a second shute wire. This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 CFR 1.72(b).
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 19, 2011
    Assignee: Varco I/P
    Inventors: Thomas Robert Larson, David Lee Schulte, Jr.
  • Method and system for controlling chemical mechanical polishing by controllably moving a slurry outlet
    Patent number: 7980922
    Abstract: A system and a method of operating a chemical mechanical polishing (CMP) system comprises a slurry delivering unit configured for locally varying the supply of slurry while polishing the substrate. To this end, the slurry delivering unit may comprise at least one slurry outlet over a polishing pad of the CMP system, wherein the at least one slurry outlet is controllably movable to distribute slurry over the polishing pad.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: July 19, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Axel Kiesel, Uwe Stoeckgen, John Lampett, Heiko Wundram
  • Method and apparatus for employing previous test insertion results for testing a device
    Patent number: 7983871
    Abstract: A method includes determining at least a first characteristic of a device during a first test insertion and storing the first characteristic. The device is identified during a second test insertion. The first characteristic is retrieved responsive to the identification of the device. A test program for the second insertion is configured based on the first characteristic. The configured test program is executed to test the device during the second test insertion.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: July 19, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas C. Kimbrough, Michael A. Retersdorf, Kevin R. Lensing
  • Method and apparatus for reducing setups during test, mark and pack operations
    Patent number: 7983778
    Abstract: A method includes determining production targets for devices of different types in a production line. A queue level of devices of a first type that have completed performance of a first operation configured in accordance with a first setup state in the production line and await performance of a second operation in the production line is determined. Based on the determined queue level, a second type of device is selected for subsequent processing in the first operation based on the production targets and a setup time associated with configuring the first operation from the first setup state to a second setup state associated with the second type of device. The first operation is configured in accordance with the second setup state for processing devices of the second type.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: July 19, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Peng Qu