Patents Represented by Attorney Williams, Morgan and Amerson
  • Patent number: 8050793
    Abstract: A method includes providing a design data file specifying at least one target feature on a first reticle. A reticle qualification data file specifying a plurality of feature measurements associated with features formed using the first reticle is provided. At least one of the feature measurements is linked to the target feature on the first reticle. The target feature and the linked feature measurement are stored in a data store.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Andrew Haskins, Chunliang Xia
  • Patent number: 8048811
    Abstract: By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be performed with a high degree of etch selectivity during the patterning of openings in a metallization layer of a semiconductor device.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Frank Feustel, Thomas Werner, Juergen Boemmels
  • Patent number: 8047295
    Abstract: In one illustrative embodiment, the present invention is directed to a device adapted to be positioned adjacent an end of a tool housing of a subsea lubricator, wherein the device includes a structural member that is adapted to be positioned adjacent an end of the tool housing, a non-metallic body coupled to the structural member and a sealing device that is adapted to sealingly engage a wireline extending through the sealing device. The present invention is also directed to a method which includes lowering an assembly toward a tool housing of a subsea lubricator positioned subsea using a wireline for the tool to support a weight of the assembly, wherein the assembly includes a wireline tool and a device including a structural member that is adapted to be positioned adjacent the end of a tool housing, a non-metallic body coupled to the structural member, and a sealing device that is adapted to sealingly engage a wireline extending through the sealing device.
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: November 1, 2011
    Assignee: FMC Technologies, Inc.
    Inventors: Brian Skeels, Hans Jørgen Lindland, Olav Inderberg, Bjørn Jahnsen
  • Patent number: 8047762
    Abstract: By providing an overhead buffer system between an automatic transport system and a load port assembly of a process tool, the efficiency of the respective load ports may be significantly enhanced, for instance, by reducing the idle time of empty carriers, thereby providing the potential for covering a wider range of operational scenarios compared to conventional strategies. For instance, for the same number of load ports, the overhead buffer system may provide a continuous operation, even if small lot sizes are used. The buffer system may comprise a dedicated transport mechanism for directly serving the load ports and respective buffer places, while respective transfer places may provide direct interaction with the automated transport system.
    Type: Grant
    Filed: February 18, 2008
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Olaf Zimmerhackl, Alfred Honold, Jan Rothe
  • Patent number: 8048748
    Abstract: In sophisticated approaches for forming high-k metal gate electrode structures in an early manufacturing stage, a threshold adjusting semiconductor alloy may be deposited on the basis of a selective epitaxial growth process without affecting the back side of the substrates. Consequently, any negative effects, such as contamination of substrates and process tools, reduced surface quality of the back side and the like, may be suppressed or reduced by providing a mask material and preserving the material at least during the selective epitaxial growth process.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Berthold Reimer, Richard Carter, Fernando Koch, Gisela Schammler
  • Patent number: 8048792
    Abstract: In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Sven Beyer, Klaus Hempel, Andreas Ott, Stephan Kruegel
  • Patent number: 8047303
    Abstract: Methods and systems for installing a drawworks on a drilling rig, the method, in certain aspects, including moving a drawworks on movement apparatus on the ground adjacent a drill floor of a rig, connecting the drawworks to the drill floor, moving the movement apparatus away from the rig, and raising the drill floor with the drawworks thereon using raising apparatus of a rig substructure supporting the drill floor. This abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims, 37 C.F.R. 1.72(b).
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 1, 2011
    Assignee: National Oilwell Varco L.P.
    Inventors: Robert Benjamin Donnally, Chunqiao Ren, Stuart Arthur Lyall McCurdy, Xi Lin Liu, Hui Chun Sheng, Yan Yu
  • Patent number: 8048330
    Abstract: By providing an interlayer dielectric material with different removal rates, a desired minimum material height above gate electrode structures of sophisticated transistor devices of the 65 nm technology or 45 nm technology may be obtained. The reduced removal rate above the gate electrode may thus provide enhanced process robustness during the planarization of the interlayer dielectric layer stack prior to the formation of contact elements.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ralf Richter, Thomas Foltyn, Anthony Mowry
  • Patent number: 8048736
    Abstract: By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which may enable a high degree of compatibility for forming via openings in a metallization layer while providing a capacitor dielectric of a desired high dielectric constant in the capacitor.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
  • Patent number: 8048726
    Abstract: In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: November 1, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Heinrich, Kai Frohberg, Sven Mueller, Kerstin Ruttloff
  • Patent number: 8051093
    Abstract: A method includes defining a general query for extracting data from at least one data store operable to store workpiece data associated with the processing of workpieces in a manufacturing system. The general query specifies at least one ambiguous parameter having a plurality of potential values. Metadata associated with the workpiece data is accessed. The metadata is employed to identify a plurality of candidate values for the at least one ambiguous parameter. A plurality of atomic queries is generated. Each atomic query is associated with one of the candidate values. The plurality of atomic queries is executed to extract data from the at least one data store and generate an output report including the extracted data.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: George M. Kaupas, Sundeep Kunchala, Andrew P. Haskins
  • Patent number: 8051301
    Abstract: A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check unit (SCU) receiving a linear address generated during execution of a current instruction. The linear address has a corresponding physical address residing within a selected memory page. The SCU uses the linear address to access one or more security attribute data structures located in the memory to obtain a security attribute of the selected memory page. The SCU compares a numerical value conveyed by a security attribute of the current instruction to a numerical value conveyed by the security attribute of the selected memory page, and produces an output signal dependent upon a result of the comparison. The MMU accesses the selected memory page dependent upon the output signal.
    Type: Grant
    Filed: November 13, 2001
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Brian C. Barnes, Geoffrey S. Strongin, Rodney W. Schmidt
  • Patent number: 8048796
    Abstract: In a sophisticated metallization system of a semiconductor device, air gaps may be formed in a self-aligned manner on the basis of a sacrificial material, such as a carbon material, which is deposited after the patterning of a dielectric material for forming therein a via opening. Consequently, superior process conditions during the patterning of the via opening and the sacrificial material in combination with a high degree of flexibility in selecting appropriate materials for the dielectric layer and the sacrificial layer may provide superior uniformity and device characteristics.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: November 1, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Robert Seidel, Thomas Werner
  • Patent number: 8043956
    Abstract: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: October 25, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Matthias Lehr, Frank Kuechenmeister
  • Patent number: 8039878
    Abstract: By appropriately orienting the channel length direction with respect to the crystallographic characteristics of the silicon layer, the stress-inducing effects of strained silicon/carbon material may be significantly enhanced compared to conventional techniques. In one illustrative embodiment, the channel may be oriented along the <100> direction for a (100) surface orientation, thereby providing an electron mobility increase of approximately a factor of four.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Igor Peidous, Thorsten Kammler, Andy Wei
  • Patent number: 8040497
    Abstract: By encoding process-related non-uniformities, such as different height levels, which may be caused by CMP or other processes during the fabrication of complex device levels, such as metallization structures, respective focus parameter settings may be efficiently evaluated on the basis of well-established CD measurement techniques.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thomas Werner, Frank Feustel, Kai Frohberg
  • Patent number: 8039342
    Abstract: In a process strategy for forming sophisticated high-k metal gate electrode structures in an early manufacturing phase, the dielectric cap material may be removed on the basis of a protective spacer element, thereby ensuring integrity of a silicon nitride sidewall spacer structure, which may preserve integrity of sensitive gate materials and may also determine the lateral offset of a strain-inducing semiconductor material.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 18, 2011
    Assignee: GlobalFoundries Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel, Thilo Scheiper, Andy Wei
  • Patent number: 8039338
    Abstract: By incorporating nitrogen into the P-doped regions and N-doped regions of the gate electrode material prior to patterning the gate electrode structure, yield losses due to reactive wet chemical cleaning processes may be significantly reduced.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Manfred Horstmann, Peter Javorka, Karsten Wieczorek, Kerstin Ruttloff
  • Patent number: 8039398
    Abstract: Prior to performing a CMP process for planarizing a metallization level of an advanced semiconductor device, an appropriate cap layer may be formed in order to delay the exposure of metal areas of reduced height level to the highly chemically reactive slurry material. Consequently, metal of increased height level may be polished with a high removal rate due to the mechanical and the chemical action of the slurry material, while the chemical interaction with the slurry material may be substantially avoided in areas of reduced height level. Therefore, a high process uniformity may be achieved even for pronounced initial surface topographies and slurry materials having a component of high chemical reactivity.
    Type: Grant
    Filed: October 3, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Feustel, Robert Seidel, Juergen Boemmels
  • Patent number: 8041339
    Abstract: A method for authenticating a mobile device is provided. The method includes receiving a communication request from the mobile device. The mobile device is operable to exchange data over a primary channel. Authentication data is received from the mobile device over a second channel. The secondary channel is a short-range channel operable for exchanging data when the mobile device is within physical proximity. The authentication data is processed to determine whether the mobile device is a trusted device.
    Type: Grant
    Filed: January 31, 2006
    Date of Patent: October 18, 2011
    Assignee: Alcatel Lucent
    Inventors: Harold Wilhelm Antonie Teunissen, Jacco Brok, Ko Marcus Joannes Louis Lagerberg, Miroslav Zivkovic