Patents Represented by Attorney Williams, Morgan and Amerson

Find this attorney in the Justia Lawyer Directory

  • Semiconductor device including a reduced stress configuration for metal pillars
    Patent number: 8039958
    Abstract: In a metallization system of a sophisticated semiconductor device, metal pillars may be provided so as to exhibit an increased efficiency in distributing any mechanical stress exerted thereon. This may be accomplished by significantly increasing the surface area of the final passivation layer that is in tight mechanical contact with the metal pillar.
    Type: Grant
    Filed: October 8, 2009
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander Platz, Matthias Lehr, Frank Kuechenmeister
  • Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier deposition
    Patent number: 8039400
    Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Koschinsky, Matthias Lehr, Holger Schuehrer
  • Intelligent document scanning
    Patent number: 8041126
    Abstract: A method, apparatus, and system, for scanning a first portion of a data to generate a second portion of data is provided. A control parameter relating to a level of detail associated with filtering a first portion of data is received. The filtering of the first portion of data is performed based upon the control parameter. The filtering of the first portion of data includes a rule-based filtering, a context-based filtering, a statistical-based filtering, or a semantic-based filtering. Performing the filtering provides for a reduction of a portion of the first portion of data. A second portion of data that is smaller than the first portion of data is provided based upon the filtering of the first portion of data.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: October 18, 2011
    Assignee: Apple Inc.
    Inventors: Devang K. Naik, Kim E. A. Silverman
  • Method and system for reducing overlay errors in semiconductor volume production using a mixed tool scenario
    Patent number: 8039181
    Abstract: By taking into consideration the combination of the substrate holders in various lithography tools used during the imaging to two subsequent device layers, enhanced alignment accuracy may be accomplished. Furthermore, restrictive tool dedications for critical lithography processes may be significantly relaxed by providing specific overlay correction data for each possible process flow, wherein, in some illustrative embodiments, a restriction of the number of possible process flows may be accomplished by implementing a rule for selecting a predefined substrate holder when starting the processing of an associated group of substrates.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Rolf Seltmann, Jens Busch, Uwe Schulze
  • Technique for forming embedded metal lines having increased resistance against stress-induced material transport
    Patent number: 8039395
    Abstract: An alloy forming dopant material is deposited prior to the formation of a copper line, for instance by incorporating the dopant material into the barrier layer, which is then driven into the vicinity of a weak interface by means of a heat treatment. As indicated by corresponding investigations, the dopant material is substantially transported to the weak interface through grain boundary regions rather than through the bulk copper material (copper grains), thereby enabling moderately high alloy concentrations in the vicinity of the interface while maintaining a relatively low overall concentration within the grains. The alloy at the interface reduces electromigration along the interface.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: October 18, 2011
    Assignee: Globalfoundries Inc.
    Inventors: Moritz-Andreas Meyer, Hans-Juergen Engelmann, Ehrenfried Zschech, Peter Huebler
  • Method and apparatus for identifying broken pins in a test socket
    Patent number: 8040140
    Abstract: A method includes scanning a test socket after removal of a device under test to generate scan data. The scan data is compared to reference data. A presence of at least a portion of a pin in the test socket is identified based on the comparison. A test system includes a test socket, a scanner, and a control unit. The test socket is operable to receive devices under test. The scanner is operable to scan a test socket after removal of a device under test to generate scan data. The control unit is operable to compare the scan data to reference data and identify a presence of at least a portion of a pin in the test socket based on the comparison.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Matthew S. Ryskoski, Christopher L. Wooten, Song Han, Douglas C. Kimbrough
  • Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain
    Patent number: 8039335
    Abstract: By forming a substantially continuous and uniform semiconductor alloy in one active region while patterning the semiconductor alloy in a second active region so as to provide a base semiconductor material in a central portion thereof, different types of strain may be induced, while, after providing a corresponding cover layer of the base semiconductor material, well-established process techniques for forming the gate dielectric may be used. In some illustrative embodiments, a substantially self-aligned process is provided in which the gate electrode may be formed on the basis of layer, which has also been used for defining the central portion of the base semiconductor material of one of the active regions. Hence, by using a single semiconductor alloy, the performance of transistors of different conductivity types may be individually enhanced.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: October 18, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Sven Beyer, Manfred Horstmann, Patrick Press, Wolfgang Buchholtz
  • Determining die test protocols based on process health
    Patent number: 8041518
    Abstract: A method includes receiving a first set of parameters associated with a subset of a plurality of die on a wafer. A die health metric is determined for at least a portion of the plurality of die based on the first set of parameters. The die health metric includes at least one process component associated with the fabrication of the die and at least one performance component associated with an electrical performance characteristic of the die. At least one of the die is tested. A protocol of the testing is determined based on the associated die health metric.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: October 18, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Michael G. McIntyre, Kevin R. Lensing
  • Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region
    Patent number: 8034669
    Abstract: The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of different strain levels obtained by providing at least one embedded semiconductor alloy in the active region, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices, in which a pronounced variation of the transistor width is conventionally used to adjust the ratio of the drive currents for the pull-down and pass transistors.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Jan Hoentschel
  • Methods of counter-doping collector regions in bipolar transistors
    Patent number: 8035196
    Abstract: The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: October 11, 2011
    Assignee: Zarlink Semiconductor (US) Inc.
    Inventors: Thomas J. Krutsick, Christopher J. Speyer
  • Transistor with asymmetric silicon germanium source region
    Patent number: 8035098
    Abstract: The present invention is directed to a transistor with an asymmetric silicon germanium source region, and various methods of making same. In one illustrative embodiment, the transistor includes a gate electrode formed above a semiconducting substrate comprised of silicon, a doped source region comprising a region of epitaxially grown silicon that is doped with germanium formed in the semiconducting substrate and a doped drain region formed in the semiconducting substrate.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: October 11, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jian Chen, James F. Buller, Akif Sultan
  • Interlayer dielectric material in a semiconductor device comprising a doublet structure of stressed materials
    Patent number: 8034726
    Abstract: By forming a buffer material above differently stressed contact etch stop layers followed by the deposition of a further stress-inducing material, enhanced overall device performance may be accomplished, wherein an undesired influence of the additional stress-inducing layer may be reduced in device regions, for instance, by removing the additional material or by performing a relaxation implantation process. Furthermore, process uniformity during a patterning sequence for forming contact openings may be enhanced by partially removing the additional stress-inducing layer at an area at which a contact opening is to be formed.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: October 11, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ralf Richter, Michael Finken, Joerg Hohage, Heike Salz
  • Architecture to support network-wide multiple-in-multiple-out wireless communication
    Patent number: 8032183
    Abstract: The present invention provides a method of coordinating transmission by and reception by a plurality of antennas associated with a plurality of radio heads. The method includes determining, at a controller, at least one relative time delay associated with a plurality of backhaul links between the controller and the plurality of radio heads. The method also includes providing information indicative of a first signal over the plurality of backhaul links. The method further includes providing timing information over the plurality of backhaul links. The timing information is determined based on the relative time delay(s) such that the plurality of radio heads can use the provided timing information to coherently transmit the first signal using the plurality of antennas and a plurality of controllers to receive mobile unit transmitted information.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: October 4, 2011
    Assignee: Alcatel Lucent
    Inventor: Ashok N Rudrapatna
  • Structured strained substrate for forming strained transistors with reduced thickness of active layer
    Patent number: 8030148
    Abstract: In a strained SOI semiconductor layer, the stress relaxation which may typically occur during the patterning of trench isolation structures may be reduced by selecting an appropriate reduced target height of the active regions, thereby enabling the formation of transistor elements on the active region of reduced height, which may still include a significant amount of the initial strain component. The active regions of reduced height may be advantageously used for forming fully depleted field effect transistors.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 4, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jan Hoentschel, Andy Wei, Sven Beyer
  • Connection manager with location learning
    Patent number: 8032150
    Abstract: A method for configuring a mobile device including a plurality of communication interfaces is provided. A first network configuration identifying communication networks accessible through the communication interfaces of the mobile device is identified. The first network configuration is compared to a plurality of previously encountered network configurations. A location of the mobile device associated with the first network configuration is designated responsive to the first network configuration being included in the plurality of previously encountered network configurations. Usage patterns of the communication interfaces at the designated location are tracked. Connectivity is established for the mobile device to a remote network through the communication interfaces based on the usage patterns.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 4, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Terry L. Cole
  • Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer
    Patent number: 8030209
    Abstract: During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 4, 2011
    Assignee: GLOBALFOUNDDRIES Inc.
    Inventors: Thomas Werner, Kai Frohberg, Frank Feustel
  • Recessed drain and source areas in combination with advanced silicide formation in transistors
    Patent number: 8026134
    Abstract: During the manufacturing process for forming sophisticated transistor elements, the gate height may be reduced and a recessed drain and source configuration may be obtained in a common etch sequence prior to forming respective metal silicide regions. Since the corresponding sidewall spacer structure may be maintained during the etch sequence, controllability and uniformity of the silicidation process in the gate electrode may be enhanced, thereby obtaining a reduced degree of threshold variability. Furthermore, the recessed drain and source configuration may provide reduced overall series resistance and enhanced stress transfer efficiency.
    Type: Grant
    Filed: August 28, 2009
    Date of Patent: September 27, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Andy Wei, Jan Hoentschel, Thilo Scheiper
  • High efficiency transmitter for wireless communication
    Patent number: 8026762
    Abstract: The present invention provides an amplifier for a wireless transmitter. In one embodiment, the amplifier includes a signal separator for decomposing an input signal into constant envelope signals and amplifier circuits for amplifying the constant envelope signals. The amplifier also includes a combiner for combining the amplified constant envelope signals to form an output signal that is an amplified representation of the input signal. Linear correction circuits are used to apply gain, phase, and/or delay correction to the constant envelope signals. The corrections are determined based upon a feedback portion of the output signal. Pre-distortion circuits are used to apply a non-linear pre-distortion to the constant envelope signals. The non-linear pre-distortion is determined based upon the feedback portion of the output signal.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: September 27, 2011
    Assignee: Alcatel Lucent
    Inventor: Walter Honcharenko
  • Method of forming CMOS device having gate insulation layers of different type and thickness
    Patent number: 8021942
    Abstract: In the process sequence for replacing conventional gate electrode structures by high-k metal gate structures, the number of additional masking steps may be maintained at a low level, for instance by using highly selective etch steps, thereby maintaining a high degree of compatibility with conventional CMOS techniques. Furthermore, the techniques disclosed herein enable compatibility to front-end process techniques and back-end process techniques, thereby allowing the integration of well-established strain-inducing mechanisms in the transistor level as well as in the contact level.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: September 20, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andy Wei, Andrew Waite, Martin Trentzsch, Johannes Groschopf, Gunter Grasshoff, Andreas Ott
  • Starch-containing compositions for use in imparting oil or grease resistance to paper
    Patent number: 8017249
    Abstract: Herein disclosed is a composition containing a thinned starch having from about 0.1 wt % to about 10 wt % substitution with a hydrophobic substituent wherein, after cooking at from about 15% solids to about 30% solids, the composition has a viscosity of about 1000 cps at 35° C. Also disclosed herein is a paper product containing a substrate containing paper or paperboard and having a first surface and a second surface and a coating applied at least to substantially the entire first surface of the substrate, wherein the coating contains a thinned starch having from about 0.1 wt % to about 10 wt % substitution with a hydrophobic substituent wherein, after cooking at from about 15% solids to about 30% solids, the coating has a viscosity of about 1000 cps at 35° C., wherein the paper product contains from about 5 lb starch to about 500 lb starch per ton of substrate.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: September 13, 2011
    Assignee: Tate & Lyle Ingredients Americas LLC
    Inventor: Patricia S. Tippit