Abstract: A flash memory array having improved core field isolation in select gate regions via shallow trench isolation and field isolation implant after liner oxidation is disclosed. The flash memory array includes a core area and a periphery area, wherein the core area further includes a select gate region. The method of fabricating the flash memory array begins by patterning a layer of nitride over a substrate in active device locations. After the nitride is patterned, a silicon trench etch is performed to form trenches. After forming the trenches, a layer of liner oxide is grown in the trenches. Then, a field implant is performed in both the core area and periphery area to provide field isolation regions for the flash memory array with. Thereafter, poly1 is patterned in the core area to form floating gate and select word-lines.

Abstract: A method and system for utilizing bits in a collection of illegal op codes in order to enable pre-decoded instructions to be stored in an instruction cache without increasing the number of bits required to represent the pre-decoded instructions. Upon fetching an instruction from memory, the op code is examined for membership in a collection of illegal op codes. If the instruction op code is a member of this collection, the instruction may be re-encoded to use a different, common illegal op code. If the instruction op code is not a member of the collection of illegal op codes, but is instead an instruction to be stored in the instruction cache in a pre-decoded format, the additional pre-decoded information may be stored in the instruction encoding by utilizing the portion of the op code space which has been vacated by the re-encoding of the illegal op codes.

Abstract: A method and system for performing backside analysis on a silicon-on-insulator (SOI) device is disclosed. The SOI device includes a silicon layer, a buried oxide layer (BOX), an active layer containing active devices, and multiple metal layers. The method includes opening a window in the silicon layer using the BOX layer as a stop, and using the window as a field of view to view structures in the active layer with a microscope, wherein defects can be detected in the device without delayering any of the metal layers, such that the device remains functional for testing.

Abstract: A method and system for determining a mask for fabricating semiconductor device is described. The method and system include patterning a resist layer on at least one mask material to provide a patterned resist layer. The patterned resist layer has a plurality of apertures therein. The plurality of apertures is for the plurality of features. The plurality of apertures has a plurality of apertures sizes and a plurality of aperture pitches. The method and system also include providing a test mask for a plurality of features using the resist layer. The test mask has the plurality of apertures therein. The method and system also include determining a plurality of flow rates for the plurality of aperture pitches and the plurality of aperture sizes based upon the plurality of features.

Abstract: A voltage controlled oscillator (VCO) is constructed using a series ring connection of an odd number K of logic inverters where K is greater than three. Each sequence of three of the logic inverters has voltage controlled feed-forward conduction circuit coupled in parallel. Each of the feed-forward circuits has the same phase between its input and output as the path it parallels. The control voltage of the feed-forward circuits operates to decrease the path delay of the logic inverters when they are conducting. Selectable inverters are connected in parallel with each logic inverter using a P and an N channel field effect transistor (FET). The N channel FET is controlled with a Mode signal and the P channel FET is controlled by a Modeb signal which is generated by inverting the Mode signal. The Mode and Modeb signals control the connection of the selectable inverters are in parallel with the logic inverters thus increasing the drive capability of the parallel combination of inverters.

Abstract: A method for evaluating the effect of crystalline originated pits (COP's) in a silicon substrate on semiconductor devices method locates a first test structure created on a COP on the substrate and a second test structure created on the substrate but not on a COP. The electrical properties of the first and second test structure are then examined and compared. If there is a difference in their electrical properties, then the COP would affect a structure similar to the test structures of a semiconductor device. In this manner, the effects of COP's on the yield for the substrate can be understood.

Abstract: A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.

Abstract: A method for filling an isolation trench structure during a semiconductor fabrication process is disclosed. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of between 100 and 400 Angstroms, and preferably 200 Angstroms. Depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of defects at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.

Abstract: A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.

Abstract: A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also include providing a lightly doped source and drain implant and a N+ source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask. Moreover, CoSi formed on the source region provides a lower resistence for lines connecting the sources, allowing a lower dose to be used for the N+ source and drain implant.

Abstract: An Audio Encoder/Decoder (AC)-97 protocol link is used for concurrent data communication between AC-97 protocol devices and non-AC-97 protocol devices. The Tag data in an AC-97 data frame is used to select specific CODECs and to determine which data time slots to ignore or accept. Since telephone voice and data communication uses only the Tag data and one other of the data frame time slots, eleven slots are available for communication using non-AC-97 protocol devices concurrent with telephony communications. Ethernet, Home Phoneline Network Alliance (HPNA), Attachment Unit Interface (AUI) are some of the data communication protocols that may be employed using embodiments of the present invention. An AC-97 data communication controller may modified with additional logic and control lines to support additional features of non-AC-97 protocol devices.

Abstract: A data processing system and method are provided for using URLs to access files located on the Internet in a similar manner used to access local files.

Abstract: A trace array for recording states of signals includes N-storage locations for k trace signals. In the write mode, an address generator combines the outputs of an event signal counter and a cycle clock counter to generate trace array addresses. A start code is written each time an event signal occurs and event addresses are saved. Recording is stopped by a stop signal and the stop address is saved. A compression code and time stamp code are written when no state changes occur in any trace signals at the cycle clock times to compress recorded trace signal data. An output processor reads out stored states of the trace signals and uses the start codes, event addresses, stop address, compression code and time stamp to reconstruct the original trace signal sequences for analysis.

Abstract: A global sign-on mechanism (GSO) is implemented. The mechanism provides a GSO system and method for a networked data processing system within an open architecture framework. The system and method are constructed on a Lightweight Directory Access Protocol (LDAP) framework by defining a set of data structures, the GSO LDAP schema. GSO functionality is effected using protocol operations on the LDAP object and attribute instances as defined in accordance with the GSO schema.

Abstract: A multiplexed grid structure for electron emission displays allows each of the grid portions to be independently controllable from each other so that electrons can be emitted from their respective pixel sites as each grid portion is addressed.

Abstract: The present invention is directed toward cathodes and cathode materials comprising carbon nanotubes (CNTs) and particles. The present invention is also directed toward field emission devices comprising a cathode of the present invention, as well as methods for making these cathodes. In some embodiments, the cathode of the present invention is used in a field emission display. The invention also comprises a method of depositing a layer of CNTs and particles onto a substrate to form a cathode of the present invention, as well as a method of controlling the density of CNTs used in this mixed layer in an effort to optimize the field emission properties of the resulting layer for field emission display applications.

Abstract: The present invention discloses a lock indicator circuit used to indicate a phase lock condition between logic signals. The lock indicator circuit uses a phase detector that generates a pulse width proportional to the phase difference between a reference signal and a feedback signal. Another circuit generates, on each positive edge of the reference and the feedback signals, pulses whose widths are primarily dependent on fixed delay elements. These fixed pulse determine a window in which the pulse from the phase detector will fall as the two signals approach phase lock. Phase lock is signaled by the logic AND of the window pulse and the phase detector pulse. Other circuitry generates a phase lock indication signal if the phase lock signal remains true for a number of consecutive transitions of the reference signal. Likewise a phase unlock indication signal is generated if after phase lock indication, phase unlock occurs and remains for a number of consecutive transitions of the reference signal.

Abstract: A method, computer program product and data processing system for verifying cumulative ordering. In one embodiment of the present invention a method comprises the step of selecting a memory barrier instruction issued by a particular processor. The method further comprises selecting a first cache line out of a plurality of cache lines to be paired with one or more of the remaining of the plurality of cache lines. If a load memory instruction executed after the memory barrier instruction in the first cache line was identified, then the first cache line selected will be paired with a second cache line. If a load memory instruction executed before the memory barrier instruction in the second cache line was identified, then a pair of load memory instructions has been identified. Upon identifying the second load memory instruction, a first and second reload of the first and second cache lines are identified.

Abstract: A videoconferencing apparatus and method are implemented. Each participant in the videoconference has a representation within the system as a “stick figure,” or linear frame, object similar to “stick figure” objects in the computer animation art. A participant's linear frame object is endowed with the persona of the participant by wrapping the object with an outer texture generated from a preloaded image of the participant. Small tags placed at preselected locations on each participant are detected by the videoconferencing system, and each of the participants stick figures is animated in accordance with changes in positions as revealed by the tags.

Abstract: For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.