Abstract: Via holes are formed in an electrically conductive power plane. Photo-imageable dielectric (PID) material is applied to one side of the power plane filling the via holes. The power plane side with no PID material is exposed to light energy to cure the PID material in the via holes. A developer is used to remove any uncured PID material. Signal plane assemblies comprising a conductive signal plane and a dielectric layer are laminated onto the filled power plane forming a two signal and one power plane (2S1P) structure. In another embodiment, the power plane has PID material applied from both sides. A photo-mask is applied to the power plane and the PID material in the via holes is cured with light energy. A developer is used to remove uncured PID material. Signal plane assemblies, as described above, are laminated onto the filled power plane forming a 2S1P structure.
Type:
Grant
Filed:
April 23, 2003
Date of Patent:
May 25, 2004
Assignee:
International Business Machines Corporation
Inventors:
Anilkumar C. Bhatt, Ashwinkumar C. Bhatt, Subahu D. Desai, John M. Lauffer, Voya R. Markovich, Thomas R. Miller
Abstract: A planar transistor structure is disclosed that minimizes resistance in the source region and simplifies fabrication of the semiconductor device. The device includes a row of transistors where each transistor includes a stack gate structure and a drain, and a layer of type-2 polysilicon is used to interconnect the transistors in each row. A source region is provided adjacent to the layer of type-2 polysilicon that includes a contact and a N-type junction extending across the source region that provides a planar electrical path between the drains of the transistors and the contact, thereby reducing resistance of the source region.
Abstract: Embossed microstructures within a substrate are used to create narrow and deep holes within that substrate. A carbon nanotube solution or mixture is then deposited over this substrate with the embossed holes. Shaking or vibrating the substrate will then cause the carbon nanotubes to fall into each of the holes in such a way that all of the nanotubes within a hole will be substantially parallel to the long axis of the hole. This structure can then be combined with a gate electrode and an anode to create a field emission display device.
Abstract: A method and system for improving networking performance in networks based on lossy channels. A selected file system call 109 is redirected by sending a file request to a server over a first protocol. Data is received from the server in response to the file request over a second protocol.
Abstract: A delta-sigma modulator for driving an output stage is disclosed. The delta-sigma modulator operates between first and second voltages and includes a loop filter, a quantizer, and a feedback loop coupling an output of the quantizer and an input of the loop filter. The feedback loop includes compensation circuitry for compensating for variations in the first and second voltages in response to a measured average of the first and second voltages and a measured difference between the first and second voltages. Measuring circuitry measures the average and the difference of the first and second voltages.
Abstract: A perforated panel having a grid of perforations or holes formed at least partially therethrough for disposing hangers for holding objects thereon and having at least a black color pattern disposed on a surface thereof for camouflaging the perforations and for reducing the appearance of damage and/or stains occurring through use is provided. It is desired to have a base finish formed on the panel and a first color pattern and the black color pattern formed by spattering of paint on the panel, screen printing, or attaching a lamina having the first color pattern and the black color pattern thereon.
Abstract: A method and system for determining an operating voltage for a semiconductor device. A first plurality of lifetimes may be determined for a first plurality of semiconductor device where the polysilicon lines in each of the first plurality of semiconductor devices have the same total area but different peripheral lengths. A second plurality of lifetimes may be determined for a second plurality of semiconductor devices where the polysilicon lines in each of the second semiconductor device have the same peripheral length but different total areas. Further, the STI structures (used to separate one or more active areas) in each of the second plurality of semiconductor devices may have the same length as the STI structures (used to separate one or more active areas) in each of the first plurality of semiconductor devices. The operating voltage may be determined based on the first and second plurality of lifetimes.
Abstract: Disclosed is a system and method for enhancing the security and reliability of virtual private network (VPN) connections by manually exchanging secondary configuration information. If a compromise is detected on a main VPN tunnel, a new VPN tunnel can be created by the system administrators using the secondary configuration, stymieing attempted security violations and providing nearly continuous service to the users. A compromise may be indicative of a security breach or other problem with the VPN. The main VPN tunnel may be abandoned or fed with false data to confuse would-be intruders if the compromise is a security compromise.
Type:
Grant
Filed:
October 28, 1999
Date of Patent:
May 18, 2004
Assignee:
International Business Machines Corporation
Inventors:
Denise Marie Genty, Gerald Francis McBrearty, Shawn Patrick Mullen, Johnny Meng-Han Shieh, Ramachandran Unnikrishnan
Abstract: A method for removing unwanted header information from a frame in a network is disclosed. It includes: storing beginning bytes of the frame in a first buffer and remaining bytes in a second buffer, where a size of the first buffer is smaller than the second buffer; determining that the unwanted header information is stored in the first buffer; copying bytes of the frame after the unwanted header information that are stored in the first buffer over the unwanted header information; reporting a number of bytes of the frame stored in the first buffer to be retrieved; and retrieving the reported number of bytes of the frame stored in the first buffer and the bytes of the frame stored in the second buffer. The copying of bytes occurs exclusively in the first buffer. Thus, removing the unwanted header information requires fewer processor cycles and minimizes latency in the packet receive process.
Abstract: A digital to analog converter including a noise shaping modulator for modulating an input digital data stream, a plurality of output elements for generating a plurality of intermediate data streams from a modulated output stream from the modulator, and an output summer for summing the intermediate data streams to generate an output analog stream. The noise shaping modulator balances an edge transition rate of the output elements, such that the edge transition rate of two selected elements is approximately equal.
Abstract: An image projection system comprises an image projector, such as a film or television projector and a projection screen. The projection screen is fabricated of a substantially transparent material, such as glass or plastic. The screen of transparent material has one or more areas or portions formed therein which areas or portions may be made to be translucent upon the application of a stimulus. Once in a translucent condition, the projected image can be received and viewed on the translucent portion. A mirror can be positioned behind the projection screen so that a person can view the reflection of themselves in the mirror when the screen is transparent, and an image can be projected when the projection screen is made to be substantially translucent.
Type:
Grant
Filed:
February 21, 2003
Date of Patent:
April 27, 2004
Assignee:
SI Diamond Technology, Inc.
Inventors:
Zvi Yaniv, Michael C. Sweaton, Alexei Tikhonski
Abstract: A method and system for insulating a lower layer of a semiconductor device from an upper layer of the semiconductor device is disclosed. The method and system include providing an interlayer dielectric on the lower layer. The method and system further include providing an antireflective coating (ARC) layer. At least a portion of the ARC layer is on the interlayer dielectric. The method and system further include providing a plurality of via holes in the interlayer dielectric and the ARC layer and filling the plurality of via holes with a conductive material. The method and system further include removing the ARC layer while reducing subsequent undesirable charge gain and subsequent undesirable charge loss over the use of a chemical mechanical polish in removing the ARC layer.
Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include providing a semiconductor substrate and providing a plurality of lines separated by a plurality of spaces. Each of the plurality of spaces preferably has a first width that is less than a minimum feature size. In one aspect, the method and system include providing a reverse mask having a plurality of apertures on an insulating layer. In this aspect, the method and system also include trimming the reverse mask to increase a size of each of the plurality of apertures, removing a portion of the insulating layer exposed by the plurality of trimmed apertures to provide a plurality of trenches and providing a plurality of lines in the plurality of trenches. In a second aspect, the method and system include providing a reverse mask on the insulating layer and removing a first portion of the insulating layer exposed by the plurality of apertures to provide a plurality of trenches.
Abstract: A noise shaper includes a first feedback loop for noise shaping a first feedback signal under normal operating conditions and having a first filter with a first signal transfer function and a second feedback loop that is stable under overload conditions and has a second filter having a second signal transfer function differing from the first signal transfer function. The noise shaper also includes an output circuit block including a quantizer and steering circuitry. The quantizer includes an input simultaneously responsive to outputs of the first and second filters. The steering circuitry steers a feedback from an output of the quantizer to input of the first and second feedback loops. The steering circuitry steers feedback from output of the quantizer to inputs of the first and second feedback loops, the steering circuitry including a first output for providing the first feedback signal to the first feedback loop and a second output for providing a second feedback signal to the second feedback loop.
Abstract: A data processing system and method for managing the storage of compiled instructions used in interpretive programming language applications is implemented. As the applications are implemented in an interpreted programming language, the instructions are compiled into byte-codes to be used by a virtual machine and are subsequently stored in a memory. The data processing system and method recognize that a same application may be used repeatedly and periodically. Thus, the data processing system and method diminish the time required to compile the instructions of an interpretive programming language application, while preserving the compilation of interpretive programming code across sessions accessing the code. Additionally, the data processing system and method diminish the time required to download a Java application and, therefore, allow a user to more efficiently access Internet operations.
Type:
Grant
Filed:
November 17, 1997
Date of Patent:
April 6, 2004
Assignee:
International Business Machines Corporation
Abstract: A level shifter having a data input node, a first inverter having its input connected to the data input node, a second inverter connected to an output of the first inverter, a data output node, a latch having its output connected to the data output node, a first NFET connected between an input of the latch and a ground potential, and having its gate electrode connected to an output of the second inverter, and a second NFET connected between the data output node and the ground potential, and having its gate electrode connected to the output of the first inverter. The level shifter provides for a conversion of a data signal from a power supply domain of 1.8 volts to one of 3.3 volts.
Type:
Grant
Filed:
May 30, 2002
Date of Patent:
April 6, 2004
Assignee:
International Business Machines Corporation
Abstract: A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.
Type:
Grant
Filed:
July 29, 1999
Date of Patent:
April 6, 2004
Assignee:
International Business Machines Corporation
Inventors:
Richard Allen Kelley, Danny Marvin Neal, Steven Mark Thurber
Abstract: The present invention is a method of forming a channel device. The method comprises the steps of providing at least one active region on a substrate wherein the active region comprises a plurality of discontinuous gate structures. The method further comprises providing an ion implantation in the substrate. In accordance with the present invention, a higher Early Voltage is achieved thereby enabling halo/pocket and LDD implants to be effectively utilized in the design of analog circuitry.
Abstract: A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control signals to the first processor. An expansion unit for communicating instructions and data between the processors and a memory device has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant. The first and second ports may be granted access in accordance with a selected arbitration protocol. A duration of the memory device access grant selectably constitutes one of a preselected number of accesses and a preselected timeslice. An amplifier amplifies the decoded digital signal from the first processor.
Abstract: A method for initializing variables within class objects in a statically loaded object-oriented programming language. A two-phase flooding algorithm is utilized to initialize the core variables within each class along with those variables needed to be initialized before the core variables. An initialization algorithm is performed within each of the class objects in a recursive manner. Once a class object has begun the initialization process internally, calls to again begin the initialization process within that class object from another class object will result in a return in order to prevent duplicates of the initialization process from being performed within each of the class objects.
Type:
Grant
Filed:
September 1, 1998
Date of Patent:
March 16, 2004
Assignee:
International Business Machines Corporation