Patents Represented by Attorney Winstead, Sechrest & Minick, P.C.
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Patent number: 6762626Abstract: A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.Type: GrantFiled: April 24, 2003Date of Patent: July 13, 2004Assignee: International Business Machines CorporationInventors: Daniel Mark Dreps, Frank David Ferraiolo, Kevin Charles Gower, Gary Alan Peterson, Robert James Reese
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Patent number: 6761870Abstract: The present invention discloses the process of supplying high pressure (e.g., 30 atmospheres) CO that has been preheated (e.g., to about 1000° C.) and a catalyst precursor gas (e.g., Fe(CO)5) in CO that is kept below the catalyst precursor decomposition temperature to a mixing zone. In this mixing zone, the catalyst precursor is rapidly heated to a temperature that results in (1) precursor decomposition, (2) formation of active catalyst metal atom clusters of the appropriate size, and (3) favorable growth of SWNTs on the catalyst clusters. Preferably a catalyst cluster nucleation agency is employed to enable rapid reaction of the catalyst precursor gas to form many small, active catalyst particles instead of a few large, inactive ones. Such nucleation agencies can include auxiliary metal precursors that cluster more rapidly than the primary catalyst, or through provision of additional energy inputs (e.g., from a pulsed or CW laser) directed precisely at the region where cluster formation is desired.Type: GrantFiled: July 1, 2002Date of Patent: July 13, 2004Assignee: William Marsh Rice UniversityInventors: Richard E. Smalley, Ken A. Smith, Daniel T. Colbert, Pavel Nikolaev, Michael J. Bronikowski, Robert K. Bradley, Frank Rohmund
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Patent number: 6760867Abstract: A writeable K by P trace array with parallel inputs and outputs is incorporated within a VLSI integrated circuit. The trace array is partitioned into N sub-arrays each sub-array having M=P/N entries for the K input signals. Logic circuitry couples selected K input signals to the trace array so that M states of the K input signals may be stored in each of the N sub-arrays. A start signal enables storing of states of the K input signals at time intervals determined by a clock. The clock is counted in a counter and when M is reached the counter is reset back to an initial state. New states of the K input signals written over old states until a pre-determined event signals occurs, at which time storing the sub-array is stopped saving the stored states of the logic inputs. Writing is simultaneously started in a succeeding sub-array in the same fashion until another event signal occurs.Type: GrantFiled: March 8, 2001Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Michael Stephen Floyd, Balaram Sinharoy
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Patent number: 6760842Abstract: Disclosed is an apparatus and method to build programs from activity function units (AFUs) within a graphical environment. Each AFU is made from graphical representations of functional units (FUs). The resulting AFUs can be locked so that users cannot view proprietary and trade secret information as to how they accomplish their tasks. AFUs can be combined with other FUs and previously-created code represented in FU form to build large complex programs which are modified and added to by the user by means of manipulation of graphical elements on the computer screen without disclosing underlying coding.Type: GrantFiled: December 7, 1999Date of Patent: July 6, 2004Assignee: International Business Machines CorporationInventors: Mark Lee Miller, Michael Scott Priddy
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Patent number: 6757855Abstract: An integrated apparatus and method for testing a very large scale integration (VLSI) device is implemented. An interface between automatic test equipment (ATE) and a device under test (DUT) includes a switch and associated control logic that mediates data transfer between high speed buses coupled to the DUT. Additionally, traffic may be switched to a port connected to a bus coupled to the ATE. This bus need not operate at the full speed of the I/O buses of the DUT. The switch also couples to a static random access memory (SRAM) data cache array which may be used for delayed echo of data between ports. Additionally a logic analyzer in the interface may be used in conjunction with the switch and cache to selectively capture data transferred between the DUT and ATE. The configuration of the switch is programmable depending on the testing performed on the DUT.Type: GrantFiled: April 9, 2001Date of Patent: June 29, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Leland Freddie Rusk, Jeffrey Brinkley
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Patent number: 6755628Abstract: The invention is a component of a subsurface traveling barrel bottom anchor pump comprising a traveling valve assembly which includes: a cylindrical valve body having a lower section, the lower section having a central bore therethrough and external threads which interact with a threaded connection on a traveling barrel to removably attach the valve body to the traveling barrel; an upper section having a rod connection externally threaded for attachment to a pumping rod; a center section having a fishing neck portion and cage portion; a valve cage accommodated entirely within the internal portion of the cage portion; a valve ball positioned within the valve cage; a valve seat abutting the valve cage; and a ball and seat plug threaded into the lower section of the valve body for retaining the valve seat in the valve body.Type: GrantFiled: July 16, 2002Date of Patent: June 29, 2004Assignee: Howell's Well Service, Inc.Inventor: Kenneth Howell
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Patent number: 6754176Abstract: A scheme for sharing a channel during a contention free period of communications between two or more basic service sets (BSSs) including network components in an overlapping region of a wireless computer network. These network components in the overlapping region may be configured to communicate in contention free periods only. Such bandwidth sharing may then include transmitting within each BSS exclusively during an allocated period of time. Each BSS may include one point coordinator network component and all other network components in the BSS then inform the point coordinator of channel conditions including degradation, and the number of packets received from other BSSs.Type: GrantFiled: July 12, 2000Date of Patent: June 22, 2004Assignee: ShareWave, Inc.Inventors: Rajugopal R. Gubbi, Amar Ghori, Gregory H. Parks
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Patent number: 6752977Abstract: The present invention relates to a process for the purification of single-wall carbon nanotubes and the purified single-wall carbon nanotube material. Known methods of single-wall carbon nanotube production result in a single-wall carbon nanotube product that contains single-wall carbon nanotubes in addition to impurities including residual metal catalyst particles and amounts of small amorphous carbon sheets that surround the catalyst particles and appear on the sides of the single-wall carbon nanotubes and “ropes” of single-wall carbon nanotubes. The purification process removes the extraneous carbon as well as metal-containing residual catalyst particles. The process employs steps including a gas-phase oxidation of the amorphous carbon and subsequent liquid-phase reaction of a halogen-containing acid with the metal-containing species. Optionally, the single-wall carbon nanotube material may be annealed dry or in the presence of moisture.Type: GrantFiled: February 8, 2002Date of Patent: June 22, 2004Assignee: William Marsh Rice UniversityInventors: Richard E. Smalley, Robert H. Hauge, Wan-Ting Chiang
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Patent number: 6754749Abstract: An integrated circuit includes a microcontroller core interconnected with a peripheral component interconnect (PCI) interface configurable as a PCI host/CPU bridge when the integrated circuit is used in embedded system applications and as a PCI device when the integrated circuit is used in a hosted application. In some cases, a radio media access controller is (MAC) interconnected to the microcontroller. Also, a forward error correction (FEC) coder/decoder (CODEC) coupled to the radio MAC may be provided. Such an FEC CODEC may be configured to provide Reed-Solomon coding/decoding. Preferably, one or more communication interfaces coupled to the microcontroller are provided, each being configured to allow for interconnection of the integrated circuit with external communication channels.Type: GrantFiled: March 15, 2001Date of Patent: June 22, 2004Assignee: ShareWave, Inc.Inventors: Elias Mounsef, Raymond Chow
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Patent number: 6754784Abstract: A system 100 including a central processing unit 101 operates in response to a set of instructions for processing information. A port 134 provides access to selected circuitry forming a part of the system by an external device. A set of non-volatile programmable security elements 136 selectively enable and disable the operation of the interface to provide a private environment for processing the information.Type: GrantFiled: June 30, 2000Date of Patent: June 22, 2004Assignee: Cirrus Logic, Inc.Inventors: Gregory Allen North, Matthew Richard Perry, Brian Christopher Kircher
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Patent number: 6749827Abstract: This invention relates generally to a method for growing carbon fiber from single-wall carbon nanotube (SWNT) molecular arrays. In one embodiment, the present invention involves a macroscopic molecular array of at least about 106 tubular carbon molecules in generally parallel orientation and having substantially similar lengths in the range of from about 50 to about 500 nanometers. The hemispheric fullerene cap is removed from the upper ends of the tubular carbon molecules in the array. The upper ends of the tubular carbon molecules in the array are then contacted with a catalytic metal. A gaseous source of carbon is supplied to the end of the array while localized energy is applied to the end of the array in order to heat the end to a temperature in the range of about 500° C. to about 1300° C. The growing carbon fiber is continuously recovered.Type: GrantFiled: December 28, 2001Date of Patent: June 15, 2004Assignee: William Marsh Rice UniversityInventors: Richard E. Smalley, Daniel T. Colbert, Hongjie Dai, Jie Liu, Andrew G. Rinzler, Jason H. Hafner, Kenneth A. Smith, Ting Guo, Pavel Nikolaev, Andreas Thess
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Patent number: 6750693Abstract: A clock generator circuit includes a counter which counts edges of a received clock signal and a comparator which compares divide ratio control data with a count generated by the counter and generates an active state of a control signal in response. An output flip-flop toggles in response to the control signal and a selected edge of the received dock signal to toggle a state of an output clock signal.Type: GrantFiled: April 4, 2003Date of Patent: June 15, 2004Assignee: Cirrus Logic, Inc.Inventor: Bruce Eliot Duewer
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Patent number: 6750461Abstract: By using a large area cathode, an electron source can be made that can irradiate a large area more uniformly and more efficiently than currently available devices. The electron emitter can be a carbon film cold cathode, a microtip or some other emitter. It can be patterned. The cathode can be assembled with electrodes for scanning the electron source.Type: GrantFiled: October 2, 2002Date of Patent: June 15, 2004Assignee: SI Diamond Technology, Inc.Inventors: Richard Lee Fink, Leif Thuesen
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Patent number: 6747973Abstract: A method for computer MSE to PE tables for rate negotiation has been disclosed. The method obtains probabilistic values for packet sizes in a network and obtains BER values for each FER based on these probabilistic values. An MSE for each PE is then calculated based on the BER values to obtain the upper limit tables. The MSE values in the upper limit tables is then decreased by 2 dB to obtain the lower limit tables. The MSE to PE tables may then be used for rate negotiation as set forth in the HPNA 2.0 specification.Type: GrantFiled: January 18, 2002Date of Patent: June 8, 2004Assignee: Advanced Micro Devices, Inc.Inventors: Kishore Karighattam, Chien Meen Hwang
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Patent number: 6748381Abstract: A method and apparatus for providing a recent set of replicas for a cluster data resource within a cluster having a plurality of nodes; each of the nodes having a group services client with membership and voting services. The method broadcasts a data resource open request to the nodes of the cluster, determines a recent replica of the cluster data resource among the nodes, and distributes the recent replica to the nodes of the cluster. The apparatus is for providing a recent set of replicas for a cluster data resource. The apparatus has a cluster having a plurality of nodes in a peer relationship; each node has an electronic memory for storing a local replica of the cluster data resource. A group services client, which is executable by each node of the cluster, has cluster broadcasting and cluster voting capability.Type: GrantFiled: March 31, 1999Date of Patent: June 8, 2004Assignee: International Business Machines CorporationInventors: Ching-Yun Chao, Roger Eldred Hough, Amal Ahmed Shaheen
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Patent number: 6748497Abstract: An apparatus and method for memory transaction buffering are implemented. Read and write buffer units are provided. The read buffer unit is configured for storing at least one data value read from a memory device, and the write buffer unit is configured for storing at least one data value for writing to the memory device. The read buffer unit is operable for updating with the at least one data value for writing to the memory device in response to a write to the write buffer unit.Type: GrantFiled: November 20, 2001Date of Patent: June 8, 2004Assignee: Cirrus Logic, Inc.Inventors: Chang Yong Kang, Jun Hao
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Patent number: 6744392Abstract: A noise shaper including first and second quantizers and first and second feedback paths each providing feedback from a corresponding quantizer output. A loop filter system implements a plurality of transfer functions including a first non-zero transfer function between the first feedback path and an input of the first quantizer, a second non-zero transfer function between the first feedback path and an input of the second quantizer, a third non-zero transfer function between the second feedback path and the input of the first quantizer and a fourth non-zero transfer between the second feedback path and the input the second quantizer.Type: GrantFiled: August 2, 2002Date of Patent: June 1, 2004Assignee: Cirrus Logic, Inc.Inventor: John Laurence Melanson
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Patent number: 6745323Abstract: A system and method for recovering a global history vector is implemented. In deeply pipelined central processing unit (CPU) architecture instruction fetches may precede execution by several processor cycles. A global history vector (GHV) may be used in predicting the branches in a current fetch cycle. Fetch redirection events, such as a cache miss, or a branch misprediction may lead to loss of synchronization of instruction fetches and the GHV. To recover the GHV following a redirection event, registers are provided to hold a GHV being used to predict branches in a current fetch cycle and two subsequent GHVs. On the occurrence of a redirection event, a fetch redirection is generated. GHV update logic detects the fetch redirection and resets the current GHV to a selected one of the stored values.Type: GrantFiled: August 3, 2000Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventor: Balaram Sinharoy
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Patent number: 6745348Abstract: A method, computer program product and system for estimating the number of internationalization faults, e.g., errors, warnings, in a software program. The number of internationalization faults may be estimated by scanning a subset of the total lines of code in a software program. A first factor may be calculated based on a count and the number of faults identified in the lines of code scanned. A second factor may be calculated based on the number of faults remaining after subtracting the number of faults identified in error from the number of faults identified in the lines of code scanned as well as the number of faults identified in the lines of code scanned. An estimate of the number of faults in the entire software program may be calculated based on the first and second factor and the count of the total number of lines of code in the software program.Type: GrantFiled: June 14, 2001Date of Patent: June 1, 2004Assignee: International Business Machines CorporationInventors: Dae-Suk Chung, Gregory P. Davis, David B. Kumhyr
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Patent number: 6743361Abstract: The present invention relates in general to a method for bacterially treating small-tank toilet systems and an apparatus for using same, and in particular, bacterially treating small-tank portable toilets, such as toilet systems in airplanes, busses, campers, trains, boats, and free-standing portable toilets.Type: GrantFiled: November 27, 2000Date of Patent: June 1, 2004Assignee: Biological Systems, Inc.Inventors: Brian Doege, Saul Krell, Mark Brodowicz, Michael Cooney