Abstract: A method for fabricating a polycide self aligned contact for MOSFET devices in which the electrical isolation between the source/drain contact and gate structure is improved. In the method a gate insulator layer, a polysilicon layer, a metal silicide layer and an insulating layer are deposited on a semiconductor substrate. The insulator layer is patterned and anisotropically etched to expose the underlying metal silicide layer. The metal silicide layer is then dip etched to form an undercut beneath the insulating layer. The metal silicide and polysilicon layers are patterned with an anisotropic etch, dopants introduced into the opening to form lightly doped source/drain regions, and sidewall spacers formed on the sidewalls of the etched layers. After a dopant is introduced to form heavily doped source/drain regions, a contact structure is formed in the opening defined by the sidewall spacers.

Abstract: There is presented an improved method of fabricating an EEPROM device with a split gate. In the method, a silicon substrate is provided having spaced and parallel recessed oxide regions that isolate component regions where the oxide regions project above the top surface of the substrate. A thin gate oxide is formed on the substrate, and a first conformal layer is deposited over the gate oxide and projecting oxide regions. The substrate is then chemical-mechanically polished to remove the projections of polysilicon over the oxide regions. A silicon nitride layer is deposited on the resultant planar surface of the polysilicon, and elongated openings formed that will define the position of the floating gates that are perpendicular to the oxide regions. The exposed polysilicon in the openings in the silicon nitride are oxidized down to at least the level of the underlying silicon oxide regions, and the silicon nitride layer removed.

Abstract: A method of etching closely spaced trenches in a silicon body wherein a masked silicon body is introduced into a plasma etching apparatus. An object having an exposed silicon surface that is consumable by a plasma environment is provided in the apparatus. A reactive plasma environment is established in the apparatus which removes silicon from the body and the silicon object. The additional silicon from the object in the plasma influences the silicon removal from the body to thereby provide tapered trench side walls.

Abstract: A method for fabricating shallow trench isolation stricture wherein a surface oxide layer and a polycrystalline silicon buffer layer are formed on a semiconductor body. Openings are formed through the layers and into the body that constitute trenches. A lining oxide layer is formed on the trench and buffer layer surfaces. A thick oxide layer is deposited on the body to fill the trench, and the layer planarized by chemical-mechanical polishing. The exposed portions of the buffer layer are removed and the horizontal surface oxide layer portions removed by anisotropic etching.

Abstract: A method for fabricating a metallurgy system is described wherein a first level of metallurgy is formed, having a plurality of close uniformly spaced conductive line of a predetermined width, and wherein there are included larger gaps between the conductive lines. The areas in the larger gaps are filled with dummy lines, where the gap is equal to or greater than three times the feature size or alternatively the width of the conductive lines.

Abstract: A method for fabricating a mask for forming a metallurgy system on a semiconductor device that provides a planar top surface is described. An initial mask pattern for the metallurgy system is designed that includes operative conductive lines that electrically connect device structure, and include parallel lines that are non-uniformly spaced, resulting in large areas. The mask design is re-designed to fill in parallel dummy lines in the large areas where the spacing of the conductive lines is equal to or greater than three times the feature size, or alternatively, the width of the lines.

Abstract: A method of cleaning an electrostatic chuck of a plasma etching apparatus wherein a dummy wafer is placed on the chuck, the chamber evacuated, and an RF voltage applied that is greater than the normal RF voltage used to etch.

Abstract: A self contained unit for forming Cu metallurgy interconnection structures on SC substrates. The unit has an enclosed chamber with a plurality of apparatus for performing wet processes, including electroless metal plating and planarization. The unit provides a way of reducing the number of times the wafer is transferred between the wet process steps that require less environmental cleanliness and dry very clean processes steps.

Abstract: An improved container for storing large diameter semiconductor wafers. The container has a body member and an enclosure member that are secured together with complimentary threaded portions. The top of the enclosure member has a circular upstanding flange spaced from a circular upstanding protrusion. Upstanding radially ribs are provided between the flange and protrusion to strengthen the enclosure member and provide a means for engagement with a wrench that will apply a torque force.

Abstract: A non-vacuum semiconductor pick-up and transfer apparatus for handling semiconductor wafers. A flat tapered blade, with front and rear arcuate abutment surfaces adapted to hold a wafer, is provided. In use the blade is thrust between spaced wafers supported in a holder, lifted to retain the wafer between the abutment surfaces, and removed from the holder. The thin and tapered blade shape minimizes damage to the associated wafers in the event of a misalignment of the blade with the wafers.

Abstract: There is described a spin coating apparatus for applying a liquid material to a semiconductor wafer, or the like, that has a spin head for supporting a wafer on the top surface, a motor to rotate the spin head, and a nozzle located over the spin head for dispensing liquid on the wafer mounted on the spin head. A liquid well is provided having a bottom outlet opening, a bottom inlet opening, a top vent opening, and a heat exchange jacket on at least the well side walls. A shut-off valve is located between the nozzle and well, with the inlet of the valve communicating with the bottom outlet of the well, and the inlet of the valve communicating with the nozzle. A liquid supply source provides liquid to the well through the inlet opening of the well. A multi-stage vent and purge system is provided to vent and selectively introduce either gas or liquid cleaning medium into the well through the top vent opening. The distance between the nozzle and the spin head is controlled with a nozzle support.

Abstract: A wafer container having an enclosure member and a body member. The body member having a base, a plurality of spaced arcuate members on the base adapted to encircle wafers stacked on the base. A layer of resilient material on the insides of the arcuate members. A retainer member with flaps positioned between the arcuate members on the top of a stack of wafers.

Abstract: There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer.

Abstract: A new combination container for wafers, and a retainer element to prevent movement of the wafers in the container, is described. The container has a body member with a circular base with a flat upper surface for supporting stacked wafers, and an upright arcuate member on the base that is adapted to encircle approximately 180.degree. of the stack of wafers. An enclosure member with a top and a cylindrical wall mates with the body member to enclose the upright member and a stack of wafers. A suitable means is provided to secure the body member and enclosure member together in sealed relationship. The wafer carrier of the invention improves the handling and storage of large diameter semiconductor wafers, is easier to load and unload, and can be opened and closed with a minimum of effort and a reduced probability of damaging the wafers.

Abstract: An improved shutter activating mechanism for an ion implantation apparatus, used to implant ions into semiconductor wafers, is described. The apparatus has an ion source, an ion accelerator, an ion beam shutter, and an ion beam shaping plate system. The improvement consists of a improved shutter activating mechanism with a rotatable shaft fixed to the ion beam shutter, a cross bar fed to the rotatable shaft, a abutment surface for limiting rotational movement of the cross bar, and a driving solenoid provided with a push rod. A bifurcated element is fixed to the end of the push rod which has aligned transverse apertures, a link joining the bifurcated element and the push rod, the link having an aperture on one end, a bearing assembly to allow limited axial movement, an a first pin through the transverse aperture and the bearing assembly. The link has a bifurcated end with transverse aperture. A second pin provides a connection between the bifurcated end of the link and the cross bar.

Abstract: There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer.

Abstract: A method of reflowing borophosphosilicate glass wherein wafers on a support that holds the wafers upright in spaced parallel relationship are introduced into a furnace. The wafers are heated to a temperature to achieve reflow while a main stream of heated inert gas is flowed over the wafers in a direction perpendicular to the planes of the substrates, while simultaneously an auxiliary stream of heated inert gas is flowed in a direction perpendicular to the main stream to prevent the formation of BPO.sub.4 crystals during reflow.

Abstract: The method requires fewer process steps. A nitride layer and a first overlying photoresist are deposited on a semiconductor substrate having wells of different impurity types. The resist layer is developed and to cover first type well and the device area of the opposite second type well. After the resultant exposed nitride layer is removed, impurity ions are implanted. The first photoresist layer is removed and a second photoresist layer deposited. The second resist layer is deposited and developed to cover the second well and the device area in the first well. The resultant exposed nitride areas are removed and ions implanted. The second photoresist layer is removed and the substrate oxidized to form field oxide regions. The nitride layer is removed and the substrate completed by forming devices, passivation layers and metallurgy.

Abstract: A process of fabricating a mask type ROM is described wherein second type impurity ions are implanted into a semiconductor substrate having a first opposite type background impurity to form a depletion region adjacent the surface. A plurality of parallel nitride lines are formed on the surface, and a first gate oxide formed on the spaces between the nitride lines. Subsequently, a first layer of doped polycrystalline silicon is deposited over the nitride lines, and the layer etched back to expose the top surfaces of the nitride lines. After the nitride lines are removed, a thin gate oxide layer is formed on the exposed surface of the substrate, and on the surfaces of the resultant first polycrystalline gate electrode lines. A second layer of doped polycrystalline silicon is deposited over the polycrystalline silicon lines, and it is etched back. The etch back of the first, and also the second polycrystalline silicon layers, produces an elongated central depression in each of the resultant lines.

Abstract: A method for dispensing fluids on a semiconductor wafer wherein a wafer is mounted on a rotatable chunk, a fluid to be dispensed is introduced into a well through an inlet located adjacent the bottom of the well, rotating the chunk and moving a soft inpact dispensing nozzle, that draws bubble-free fluid from the bottom of the well, over the wafer, and dispensing the fluid at a low pressure and a short distance to the wafer surface.