Abstract: A method of providing a stress-free metal layer by electroless plating techniques, including the steps of (1) providing a substrate that includes some glass material in at least the surface areas to receive a metal layer, (2) depositing a layer of metal-boron by electroless plating techniques, and (3) heating the resultant metal-boron layer in a non-reacting and/or H.sub.2 environment at a temperature of at least 750.degree. C. for a time sufficient to diffuse the boron to the glass material in the substrate.

Abstract: A process and a solid plane structure for minimizing delamination during sintering in the fabrication of multi-layer ceramic substrates, wherein the solid plane structure is designed to obtain maximum ceramic to ceramic interface contact.

Abstract: A dielectrically isolated semiconductor device can be manufactured. The structure is useable for integrated circuits, including field effect and/or bipolar transistors, wherein a significant savings in surface area and reduction in capacitances can be obtained over prior techniques. The method involves forming a layer of dielectric material upon a semiconductor body, having a diffused region where a bipolar device is to be formed, and then forming an opening in the layer to expose a part of the surface of the diffused region of the semiconductor body. An epitaxial layer of silicon is deposited on top. Single crystal silicon will grow over the exposed silicon area and if a diffused region is present in the substrate a pedestal will outdiffuse through the same area from the buried diffused region. Polycrystalline silicon will grow on top of the dielectric material. The pedestal is formed in a single crystal epitaxial layer of another impurity type.

Abstract: A multi-layer metallized substrate comprises a matrix of sintered silicon particles joined by a thin insulating layer of silicon dioxide or silicon nitride. Semiconductor circuit chips are bonded to the surface of the substrate to form an electrically connected, unitary integrated circuit module structure.

Abstract: A process for forming ball limiting metallurgy pad structure for a semiconductor device solder bond interconnection comprising:forming a conductive layer that is adherent to the semiconductor device passivating layer,forming a relatively thick layer of a material having a high thermal conductivity,forming a barrier layer that protects the high conductivity layer by physically preventing any interaction or alloying with the subsequent layers, andforming a layer of a material that is solder wettable.

Abstract: A process for monitoring solvent content in a ceramic green sheet wherein the green sheet is partially supported so that a portion of the sheet is free to sag under the influence of gravity, with or without any additional force to enhance or minimize the sag, measuring the rate of sag of the portion of the sheet free to sag, and comparing the rate of sag to a correlation standard of rate of sag versus solvent content of the green sheet under test to determine acceptability.

Abstract: A method or technique is disclosed for predicting precisely where oxygen precipitation will occur in semiconductor wafers that are being processed in connection with integrated circuit manufacture; the technique is based upon the discovery that such precipitation will occur at resistivity peaks measured prior to any thermal treatment of the wafers. In other words, the technique permits characterizing the wafers by the diametral resistivity profile that is obtained in the initial resistivity measurements, whereby a change in oxygen precipitation can be predicted precisely where compensated intrinsic regions have been measured in the initial measurements.

Abstract: A process for forming a substantially glass free surface on screened refractory metallurgy areas on a ceramic substrate wherein a thin layer of Pd is deposited over the metallurgy areas and the metallurgy areas subsequently sintered causing the surface refractory metal particles to be fused into a substantially solid metallurgy layer under the catalyzing influence of the Pd.

Abstract: A method of fabricating an improved multi-layer ceramic substrate for mounting semiconductor devices having a low incidence of cracks between metal filled surface vias, the substrate constructed with a top ceramic layer having a thickness that is at least 20 percent greater than the underlying sheets that embody a redistribution system.

Abstract: A process for forming a glazed ceramic substrate, more particularly for forming a particular surface finish and/or surface pattern in the glass. The process consists of preparing a ceramic mixture which includes a basic oxide, such as Al.sub.2 O.sub.3, and a glass, forming the substrate as by molding, pressing, or doctor blading and lamination, and sintering in a non-reactive atmosphere on a setter tile that is non-wettable by the glass. During the sintering operation the glass becomes molten and flows downwardly under the influence of gravity through the ceramic particles. The glass flows to the setter plate to conform to its surface configuration, forming a glazed surface on the substrate.

Abstract: The invention is a structure for improving the cooling characteristics of a silicon semiconductor device immersed in a fluid coolant. The cooling improvement is achieved by enhancing the nucleate boiling characteristics of the silicon device by initially forming lattice defects on the backside surface of the device by sandblasting and subsequently etching the damaged surface to remove the lattice defects and thereby produce an intricate surface morphology which provides nucleate boiling sites.

Abstract: A method of forming surface planarity to a substrate during removal of excess dielectric material when fabricating recessed regions of dielectric material in a semiconductor device wherein a dielectric layer is formed on the surface of the silicon substrate, a relatively thick layer of polycrystalline silicon deposited over the SiO.sub.2 layer, openings formed through the polycrystalline layer and SiO.sub.2 layer and into the substrate to form trenches, vapor depositing a layer of dielectric material over the surface of the substrate to a depth sufficient to fill the trench, depositing a planarized layer over a layer of dielectric material, reactive ion etching the planarizing layer, the dielectric layer, the polycrystalline layer, and selectively removing the remaining polycrystalline silicon layer to expose the SiO.sub.2 layer.

Abstract: An improved multi-layer ceramic substrate for mounting semiconductor devices having a low incidence of cracks between metal filled surface vias, the substrate constructed with a top ceramic layer having a thickness that is at least 20 percent greater than the underlying sheets that embody a redistribution system.

Abstract: A method of making a multi-layer ceramic substrate for an integrated circuit device package having internal circuitry by forming a plurality of porous ceramic bisque sheets, impregnating the pores of the bisque sheets with an organic binder material, forming openings through the impregnated bisque sheets, filling the openings with conductive material and imprinting conductive circuitry patterns on the surface of the impregnated bisque sheets of a conductive material, assembling the plurality of apertured printed impregnated bisque sheets into a laminated unit, and sintering the laminated unit to form a unitary laminated structure having an interconnected internal circuitry system.

Abstract: A ball limiting metallurgy pad structure for a semiconductor device solder bond interconnection comprising:a conductive layer that is adherent to the semiconductor device passivating layer,a relatively thick layer of a material having a high thermal conductivity,a barrier layer that protects the high conductivity layer by physically preventing any interaction or alloying with the subsequent layers, anda layer of a material that is solder wettable.

Abstract: A method of forming a refractory metal silicide pattern on a substrate by (1) forming a blanket layer of SiO.sub.2 on the substrate, (2) depositing a blanket layer of polycrystalline Si over the SiO.sub.2 layer, (3) defining a pattern in the blanket Si layer thereby exposing selected areas of the SiO.sub.2 layer, (4) depositing a blanket layer of refractory metal silicide on the substrate over the SiO.sub.2 and Si layers, (5) heating the substrate in an oxidizing environment to a temperature sufficient to oxidize the metal silicide layer over the Si to form an upper layer of SiO.sub.2 and to convert the metal silicide layer overlying the SiO.sub.2 layer to a metal rich SiO.sub.2 layer, andexposing the oxidized surface to an etchant that selectively etches away the metal rich SiO.sub.2 layer.

Abstract: A method of forming ceramic material which includes mullite (3Al.sub.2 O.sub.3.2SiO.sub.2) in any desired percentage. A particulate mixture is formed of (1) mullite in an amount of at least 5% by weight, (2) Al.sub.2 O.sub.3 in an amount to provide sufficient SiO.sub.2 to combine with Al.sub.2 O.sub.3 to form the desired mullite. The mixture is sintered to a temperature in the range of 1300.degree. C. to 1600.degree. C. wherein the Al.sub.2 O.sub.3 and SiO.sub.2 react to form mullite under the influence of the initially added mullite.

Abstract: A solution for dissolving noble metal alloys which include tin, and other metals commonly used in semiconductor package substrates, having significant concentrations of KI, iodine and halogen ions selected from the group consisting of chloride and bromide ions.

Abstract: A method of achieving uniform shrinkage of a laminated green ceramic substrate during sintering wherein the substrate is placed on a flat, relatively thick plate of refractory material such as molybdenum, tantalum or tungsten or alloys thereof with the flat plate provided with a thin surface coating layer of a ceramic material, and heating the substrate to a sintering temperature and maintaining the temperature for a time sufficient to sinter the substrate.A setter plate for supporting a planar green ceramic substrate during the sintering operation, the setter plate is made of a refractory material and provided with a thin ceramic coating at least on the top surface.

Abstract: A package for mounting, interconnecting, and cooling a large number of integrated circuit semiconductor devices having a sintered multilayer ceramic substrate provided with an internal metallurgy network made up of voltage planes, X and Y signal planes, and fan-out planes, with I/O pins on the bottom surface, and a plurality of asymmetrical solder pad clusters for flip chip bonding to a plurality of integrated circuit devices on the top surface, a plurality of integrated circuit devices bonded to the solder pad clusters, at least one row elongated engineering change pads surrounding each pad cluster, each pad provided with a severable surface link, the I/O pins connected to the internal network of the substrate and arranged in clusters with the powering voltages of each device located directly beneath the device thereby minimizing voltage drop, and signal voltages inputted through the I/O pins interspersed between the clusters of power pins, a cap for forming an enclosure over at least the top surface of the