Abstract: A method of forming a metallurgy system on a semiconductor substrate is provided. A first conformal layer of SiO.sub.2 is deposited on the substrate using plasma enhanced chemical vapor deposition (PECVD) techniques. Subsequently a non-conformal organic layer is deposited by spin-on-glass (SOG) techniques over the first layer, and heated to smoothen the surface. The organic SOG deposited layer is then subjected to a N.sub.2 plasma environment and a second conformal layer of SiO.sub.2 is deposited, and then vias etched through the layers. The resist layer used to define vias is removed by an O.sub.2 plasma and the device metallurgy completed.

Abstract: The invention describes recessed buried conductive regions formed in a trench in the substrate that provides a smooth surface topology, smaller devices and improved device performance. The buried regions have two conductive regions, the first on the trench sidewalls, the second on the trench bottom. In addition, two buried layers are formed between adjacent buried conductive regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the conductive regions on the trench bottoms. The first conductive region and the anti-punchthrough layer have the effect of increasing the punchthru voltage without increasing the threshold voltage. The first and second regions also lowers the resistivity of the buried regions allowing use of smaller line pitches and therefore smaller devices. Overall, the recessed conductive regions and the two buried layers allow the formation of smaller devices with improved performance.

Abstract: A process for fabricating a three-dimensional multi-chip array package wherein master semiconductor substrate is formed having a peripheral inner row of contact pads and a peripheral outer row of terminal pads. A plurality of subordinate semiconductor substrates are formed provided with a peripheral row of contact pads that match the contact pads on the master substrate. Openings are formed through centers of the contact pads that extend through the subordinate substrates. The subordinate substrates are stacked on the master substrate with the openings in alignment over the contact pads. The openings are then filled with a conductive material to interconnect the contact pads on all its substrates.

Abstract: This inventions provides a method to form metal lines with smaller line pitches than is possible using the conventional photolithographic single coating process. This invention provides for a double photolithographic process where the surface is coated, exposed and developed twice to form two sets of resist patterns. These resist patterns are used to form metal lines over all the buried bit lines. These metal lines provide better masking of the bit lines from the code implants thereby reducing bit line resistance and increasing ROM read speed.

Abstract: A process of fabricating a non-volatile read only memory device (ROM) wherein the conductive word lines have desirable very narrow widths and are closely spaced. The invention provides a process for forming word lines with a smaller width and line pitch than is possible with conventional processes. A first set of word lines is formed. Next, a second set of word lines is formed in between the first word lines using oxide spacers to define the second word lines.

Abstract: An improved structure and process of fabricating an electrically erasable programmable read only memory device (EEPROM's) wherein a thick oxide region is formed on the surface of a semiconductor substrate. The thick oxide is removed forming a depression in the surface. Impurity ions are implanted in the depression forming a highly doped tunneling region. A tunnel oxide layer is formed on the substrate surface fully covering the tunneling region. Next, the floating gate layer is formed on the tunnel oxide layer. The gate isolation layer and control gate layer are formed over the floating gate layer. Subsequently, the spaced source and drain regions are formed in the substrate on opposite sides of the gate structure. A dielectric layer is formed over the control gate region and substrate. Contact openings are formed.

Abstract: An improved electrically programmable and erasable memory device having a plurality of addressable single transistor cells, each transistor having spaced source and drain regions, a floating gate and a control gate. The improvement is a new tunneling insulator layer structure between the floating gate and the control gate. The improved tunneling layer is a dual layer formed of a outer silicon oxide layer and an inner silicon oxynitride layer.

Abstract: The container has an enclosure member and a body member which together enclose a volume to accept wafers for storage, for handling, or for transportation. The body member has a base, and a plurality of spaced upright arcuate members supported on the base that are adapted to encircle wafers stacked on the base. An enclosure member has a circular top wall and a cylindrically shaped wall that is adapted to encompass and enclose the arcuate members. The retainer element has a flat central portion, and a plurality of flexible outwardly extending flaps depending from the central portion. The retainer element fits within the arcuate members of the body member with the end portions of the flaps positioned in the slots between the arcuate members.

Abstract: A process of fabricating a double stacked trench capacitor DRAM cell and resulting DRAM cell is described. The process begins by forming a trench in a semiconductor substrate. A first insulating layer is formed on the top surface of the substrate and on the sidewalls and bottom of the trench. A first contact opening is formed in the first insulating layer. A first polysilicon layer is formed and patterned to overlay the trench surface and a portion on the surface that extends into the contact opening. An insulating layer is formed over the first polysilicon layer. A second polysilicon layer is formed and patterned over the first polysilicon layer. An insulating layer is formed over the second polysilicon layer. A second contact opening is formed in the first insulating layer. A third polysilicon layer is formed over the second polysilicon layer and a portion extending into the second contact opening.

Abstract: A manufacturing plant is described for producing semiconductors that will function at a low production level during the initial phase. The plant can be expanded to provide a greater production volume with minimum additional investment, minimum disruption to the existing manufacturing line, and can be done quickly at minimum cost. Also described is a method for building a manufacturing plant for integrated circuit devices that can be operated at a low level during the initial phase, and provides for an efficient and rapid expansion to a higher level of manufacturing with minimum cost, and disruption to the existing line.

Abstract: A method of fabricating a bipolar transistor with a buried subcollector by forming a collector layer and a base layer in a semiconductor substrate. A polysilicon layer is deposited over the base layer and spaced emitter and base contact regions formed in the base layer. A mask is formed over the emitter and base contact regions and the substrate anisotropically etched to form pedestals with vertical sidewalls. A masking layer is formed on the vertical sidewalls, and a large angle ion implant used to introduce ions beneath the collector layer, thereby forming a subcollector region.

Abstract: An improved method and resulting structures for producing a layered capacitor structure of memory cell of a DRAM device wherein a doped polysilicon spacer operates as a dopant source for an overlying polysilicon layer on the vertical and sharply inclined surfaces.

Abstract: A dielectrically isolated semiconductor device which is substantially planar can be manufactured. The structure is useable for integrated circuits wherein a significant savings in surface area can be obtained over prior techniques. The structure is particularly useful for bipolar integrated circuits wherein a semiconductor substrate with an epitaxial layer thereon contains a buried region partially in the substrate and in the epitaxial layer. The emitter and base regions are located in the epitaxial layer above the buried region. The dielectrically isolating region surrounds the emitter and base region at the surface and extends to a depth wherein it intersects with the buried region to fully isolate the device. The buried region is connected as the collector element of the transistor.

Abstract: The invention is an improved pallet clamp for positioning and holding a pallet supporting a workpiece relative to a machine adapted to operate on the workpiece. The clamp has a base member, a plurality of longitudinally movable registration pins adapted to engage bores on a pallet, a pallet support surface, jaws to engage and clamp the pallet against the support surface, and an actuation means to initially move the registration pins into the bores on the pallet and subsequently move the jaws into clamping engagement.

Abstract: A metal etching process involving an oxidation-reduction reaction where the metal being etched is oxidized and the active ingredient in the etchant solution is reduced, incorporates contacting said metal with an etching solution containing an active ingredient selected from the group consisting of ferric ions, ferricyanide ions, ceric ions, chromate ions, dichromate ions, and iodine, and introducing ozone into said etching solution to rejuvenate and agitate the solution.

Abstract: An apparatus for reflowing solder terminals that join an electronic element to a support substrate, which apparatus includes (1) a stage for supporting the substrate, (2) a quantity of liquid capable of being heated to a temperature in excess of the melting point of the solder of the solder terminals, (3) a means to contact a surface of the substrate with the liquid, including a reservoir for maintaining the liquid, and a pumping means to move the liquid from the reservoir into contact with the surface of the substrate, and (4) a means to control the temperature of the liquid when in contact with the substrate to initially increase the temperature of the liquid, and subsequently reduce the temperature of the liquid.

Abstract: A substrate for an integrated circuit semiconductor package with I/O pins joined to the bottom surface, the improvement being the combination of solder wettable pin pads on the bottom surface of the substrate, I/O pins with a diameter less than the diameters of the pin pads, and a brazing material of an alloy that includes Ag, and a metal selected from the group consisting of In and Sn, and mixtures thereof, that exhibits a mushy zone over a predetermined temperature range, the metal disposed only between the pins and pin pads.

Abstract: The process for producing microsized amorphous particles of a metal phosphate incorporates the steps offorming a solution of a metal alkoxide in an organic solvent,forming an aqueous phosphoric acid solution,introducing the alkoxide and the phosphoric acid solutions into a reactor vessel wherein the solutions are immiscible and forming two separate liquid phases with an interface,applying agitation to at least the region of the interface to promote a reaction between the metal alkoxide and said phosphoric acid at the interface,collecting the reaction product, andfiring it in an oxygen containing environment at a temperature sufficiently high to drive off the organic residue.

Abstract: A welding apparatus for bonding small wires to a metal surface wherein an electric current is passed through a portion of a wire in contact with a welding tip, the apparatus having a welding tip support means for supporting the welding tip for rectilinear movement, the support means having movable mass less than 10 grams, the low mass enabling the welding tip to maintain contact with the wire portion during the molten phase of the wire during the welding operation, and a means to urge the tip support means into engagement with the wire.

Abstract: A method of fabricating a multilayer ceramic substrate with an internal conductive metallurgy circuit network, wherein additional green sheet material is added to the stack of ceramic green sheets during assembly to areas of the substrate outside of the conductive metallurgy to compensate for the volume of conductive metal paste to thereby eliminate or minimize substrate distortion during the sintering operation. An unsintered intermediate green ceramic substrate made up of green ceramic sheets with via holes and conductive metal lines on the surface which collectively form the circuit network where the improvement is additional green ceramic material in the substrate in areas outside of the conductive metallurgy network to compensate for the additional volume of material of the conductive metal which additional material provides a more uniform ceramic material density through the substrate.