Abstract: In a semiconductor substrate having a trench isolation pattern formed therein, a method is taught for improving the planarity of the substrate and for improving the silicon nitride passivation at the trench peripheries. The quality of the trench edge is improved by providing for an undercut silicon dioxide layer and a recessed silicon sidewall arrangement below the silicon nitride layers resulting in better protection of the underlying SiO.sub.2 and Si regions. In further processing, improved planarity between the polyimide-filled trench and the adjacent substrate is achieved by establishing a polyimide etch-back point via a previously deposited oxide layer. Subsequent removal of the oxide does not affect the polyimide; the top of said polyimide being substantially planar with the adjacent substrate.

Abstract: A positive resist containing a weak base and polyvinyl phenol as a film forming component is deposited on a substrate, subsequently exposed imagewise, cured, blanket exposed and developed in a KOH solution at temperatures of less than 10.degree. C. The resist pattern thus obtained is exposed to light having a wavelength ranging from 300 to 320 nm and finally heat-treated at temperatures ranging from 150.degree. to 280.degree. C. The finished lift-off mask is dimensionally stable at temperatures of .ltoreq.280.degree. C. and does not emit liquid or volatile components when heated.During application of the lift-off mask, a material is blanket vapor deposited at a substrate temperature ranging from about 160.degree. to 250.degree. C. on the resist pattern having openings with overhanging walls. Subsequently, the resist pattern is dissolved in a sodium metasilicate solution, causing the material vapor deposited thereon to be lifted off, with the material deposited on the substrate directly remaining.

Abstract: The method of bonding metal elements to a glass or ceramic substrate that includes the steps of forming a particulate material of a eutectic composition of Cu.sub.2 O and P.sub.2 O.sub.5, combining the eutectic material with an organic vehicle and the metal elements to be bonded, and heating the combination to a temperature above the eutectic temperature of the eutectic material.

Abstract: In a semiconductor module with a substrate having a plurality of semiconductor devices mounted on the top surface, an internal metallurgy system interconnecting the devices, an auxiliary set of conductive lines with periodically occurring surface connecting terminals, engineering change terminals with electrical connections to the device terminals and to the internal metallurgy system, the improvement beingengineering change devices,terminals on the engineering change devices to establish electrical contact with the engineering change terminals and the surface connecting terminals,a tailorable metallurgy system which permits establishing selective electrical connections between individual terminals of the engineering change devices, anddeletable surface lines on the substrate to selectively electrically isolate selected engineering change terminals from the internal metallurgy.

Abstract: Automatic material identification is achieved using infrared thermometry. A focused beam of high flux energy is passed through a dichroic beam-splitter to remove visible UV with the remaining infrared directed to the surface of the material to be identified. An infrared thermometer sensor is positioned to sense the magnitude of the energy received from the material surface with the magnitude of the energy being indicative of the type of material scattering such energy. Control apparatus are employed to provide control signals as a function of the type of material identified such that automatic process operations may be effected in accordance therewith.

Abstract: A process for bonding an I/O pin to a substrate wherein a mass of brazing material of an alloy that includes Ag and a metal selected from the group consisting of In and Sn and mixtures thereof, that exhibit a mushy zone over a predetermined range, is placed between a pin pad and the bonding surface of an I/O pin, where the diameter of the pin pad exceeds the diameter of the bonding surface of the pin by at least 0.01 inches, heating the resultant assembly to a brazing temperature within the predetermined range to form a mushy state of the brazing material while applying pressure to the pin, and cooling the assembly.

Abstract: A process for removing organic materials from an article formed from a slurry of glass and/or ceramic particles, resin binder, and a solvent for the resin binder, the process involving including in the slurry a particulate catalyst selected from the group consisting of Cu, Cu.sub.2 O, CuO, Cu.sub.2 SO.sub.4, CuCl.sub.2, Cu organometallic compounds, and mixtures thereof, the catalyst promoting a rapid and complete removal from the shaped article when heated of the organic materials of the slurry.

Abstract: A unitary heat sink for a semiconductor package having a plurality of cooling fin elements, each element having upwardly extending openings that divide the base into a plurality of leg portions, the heat sink having a plurality of flat base portions individually bonded to a surface of the package, each of the leg portions of an individual fin element being integral with different but adjacent flat base portions, in operation the heat sink preventing a build-up of stresses at the bonded interface of the base portions and package due to differential coefficient of expansions of the heat sink and package.

Abstract: In accordance with the present invention, we provide a new method for relieving stresses in the device-substrate interconnection structure which greatly enhances the resistance of the interconnection solder bonds to fatigue failure. In accordance with the aforementioned object of the process of our invention for forming improved solder interconnections between integrated circuit semiconductor devices and the supporting substrate, the process includes the step of joining the device I/O pads to the corresponding I/O pads of the substrate by positioning the device over the substrate with solder material selectively positioned between the respective I/O pads, heating the assembly to at least the melting point of the solder material, and cooling to solidify the solder. Subsequently, the resultant device-substrate is annealed by heating to an annealing temperature in the range of 115.degree. to 135.degree. C. and maintaining this temperature for a time in excess of 2 days.

Abstract: A lift-off process for depositing a metallurgy layer on a substrate wherein the improvement is the use of a sacrificial masking layer that is substantially unaffected by exposure to high intensity radiation. The process includes the steps of (1) preparing a resin mixture of a polyaryl sulfone polymer, and a compound of the following: ##STR1## wherein R.sub.1 is a methyl ethyl or an .alpha. branched alkyl group from 3 to 10 atoms, R.sub.2 is a hydrogen, methyl, ethyl or a branched alkyl group of from 3 to 10 carbon atoms, and X has a value of 1 to 6, and Z is an aliphatic hydrocarbon of the formula C.sub.5 H.sub.8 the compound being present in the amount of from 0.5 to 3.

Abstract: A cooling means for a circuit chip device employs a noneutectic metal alloy to form a low thermal resistance bridging interface between the surface of the chip device and a heat sink. The alloy has a solidus-liquidus temperature range such that the solidus is slightly below the maximum operating temperature of the chip, and thus has the capability to reestablish and maintain the interface at a low thermal resistance if stressed during circuit operation, even with a low current load at the interface of the chip device and the heat sink. In addition to the chip interface, the above cooling means is also used at other interfacial regions of the heat sink, dependent on design, to achieve very low thermal resistance.

Abstract: An improved solder interconnection for forming I/O connections between an integrated semiconductor device and a support substrate having a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of the semiconductor device to a corresponding set of solder wettable pads on a substrate, the improvement being a band of dielectric organic material disposed between and bonded to the device and substrate embedding at least an outer row of solder connections leaving the center inner solder connections and the adjacent top and bottom surfaces free of dielectric material.

Abstract: A robotic apparatus having five degrees of movement with a mounting plate, a first stage platform movably mounted on the mounting plate to shift in the X direction, and also rotate about the X axis, a second stage platform movably mounted on the first stage platform to shift in the Y direction, and also rotate about the Y axis, a third stage platform movably mounted on the second stage platform to move in the Z direction, and powering means to move and rotate the aforementioned elements in the manner described.

Abstract: According to this process two partial patterns which, if superimposed upon each other in a predetermined alignment relative to each other yield the desired pattern, with elements of both partial patterns combining to form elements of the pattern, and these partial pattern elements overlapping sectionally, are projected with a suitable radiation onto the radiation-sensitive layers. Overlapping is achieved in that when designing the two partial patterns a pattern corresponding to the desired pattern is used as a basis in that the elements of this pattern are exposed to a negative windage, the negative windage pattern is subsequently partitioned into two negative windage patterns corresponding to the partial patterns, and finally the negative windage partial pattern elements are exposed to a positive windage to the desired size of the partial pattern elements.The method is used in particular when a pattern is to be transferred by means of hole masks, and if it is necessary, e.g.

Abstract: The viscosity of molybdenum paste may be predicted and controlled, by measuring and altering, respectively, the particle packing density of the molybdenum powder used in the paste. For a given vehicle, there is a low correlation between average particle size and paste viscosity, but a high direct correlation between particle packing size and paste viscosity.

Abstract: A process for forming a high density solder pad and fan-out metallurgy system in a ceramic substrate wherein a pattern of indented lines is formed in the surface of a green ceramic substrate, the lines filled with a conductive metal paste, a layer of dielectric green ceramic material deposited over at least a portion of the area of the pattern of indented lines, and sintering the resultant substrate.

Abstract: According to this method, copper is dry etched in a glow discharge containing compounds with at least one methyl or methylene group, particularly at temperatures close to room temperature.The method is applied in particular for making conductors on or in module substrates or circuit cards, solder spots, and the wiring of magnetic thin films.

Abstract: A process for forming a top surface metallurgy pattern on a green unsintered ceramic substrate including the steps of forming indented lines on the surface of the substrate, sintering the substrate, depositing a blanket layer over the top surface of the substrate with a thickness less than the depth of the indented lines, applying a masking layer over the metal layer, removing the masking layer over all portions except the indented lines, removing the exposed areas of the metal layer, and removing the remaining portions of the masking layer.

Abstract: This invention concerns a ceramic substrate for mounting semiconductor integrated circuits. The substrates include at least a first and second patterned metallization layer which respectively form conducting planes that are parallel to each other but separated by a thickness of insulation. The pattern metallization of at least the first plane includes signal conductors for joining the contacts of the integrated circuit chip to pins provided in the substrate for connecting the substrate and chip to a circuit board. In accordance with the invention, the metallization of the second plane includes shorted conductor loops that follow the contour of the signal conductors. The shorted loops of the second plane metallization includes branches which extend parallel to both lateral sides of a respective signal conductor. In accordance with the invention, the branches of the loops are joined at their ends.

Abstract: A pinless connector interposer for making densely populated, inexpensive, simple, reliable, self-wiping connections between components used in semiconductor packaging such as semiconductor carrying substrates, flexible and rigid printed circuit boards and cards. The connector interposer comprises an elastomeric base member in which deformable protrusions are formed on both the top and bottom surface of the base member, wherein the protrusions correspond to contact pads of semiconductor packaging components. An electrically conductive metal coated flexible overlay is bonded to the base member, forming electrically conductive tab elements, enabling a multitude of connections to be made to a semiconductor package. The connections can be accommodated on centers as low as 0.025 inches, despite the non-planarity that may exist between the packaging components of a system.