Abstract: A semiconductor resistor structure for providing a high value resistance particularly adapted for space charge limited transistor applications, the resistor being fabricated in a semiconductor body having a resistivity in excess of 1 ohm cm., more preferably in semiconductor material that is nearly intrinsic. The resistor has two parallel elongated surface diffused regions in the body of an impurity similar to the background impurity of the body and having a surface concentration sufficient to provide an ohmic contact, the boundaries of said surface diffused regions defined by the interface where the impurity concentration of the diffused region is ten percent more than the impurity concentration of the background impurity of the body. In a preferred embodiment, the surface diffused regions are spaced such that the boundaries intersect with each other, and ohmic contact terminals to each of the diffused regions.

Abstract: An improved method for forming a recessed thermal SiO.sub.2 isolation region in a monocrystalline silicon semiconductor body having a major surface lying in a (100) plane as defined by the Miller indices by forming an etch resistant and oxidation resistant masking layer on the major surface of the body, forming at least one rectilinear annular opening in the masking layer, the opening being oriented with the sides parallel to the [100] directions on the major surface, removing a portion of the exposed body by anisotropic chemical etching, and oxidizing the resultant exposed portions of the body until the surface of the resultant SiO.sub.2 and major surface are substantially coplanar.A semiconductor device including a silicon substrate of a first conductivity, the major surface being in the (100) plane, an epitaxial silicon layer on the substrate, a lateral PN junction in the substrate, at least one annular rectangular shaped recessed SiO.sub.

Abstract: A process for etching aluminum wherein a masked layer of aluminum, supported on a substrate, is exposed to a plasma formed by imposing an RF voltage across at least two spaced electrodes in an ambient including a gas selected from the group consisting of CCl.sub.4, Cl.sub.2, Br.sub.2, HCl. The resultant conditions provide a reactive environment where the aluminum is bombarded with chlorine or bromine ions. The aluminum reacts with chlorine or bromine ions to form an aluminum chloride or bromide compound, which is volatile at the temperature of the sputtered substrate.

Abstract: A non-volatile read mostly memory cell in a monocrystalline semiconductor body wherein the sensing of the information is achieved by measuring the substrate current.

Abstract: A process for forming an embedded interconnection metallurgy system on a substrate by (1) forming a first layer of an organic thermosetting polymerized resin material on the substrate, (2) forming a second overlying layer of a material that is soluble in a solvent that does not appreciably affect the material of the first layer, (3) forming a third layer resistant to reactive ion etching in O.sub.2 on the second layer, (4) masking the third layer to define the pattern of the desired metallurgy, (5) removing the exposed areas of the third layer, (6) reactive ion etching the resultant exposed areas of the first and second layers, (7) depositing a conductive metal with a thickness approximately matching the thickness of the first layer, and (8) exposing the substrate to a solvent selective to the material of the second layer thereby removing it and the overlying portions of the conductive metal layer.

Abstract: A dual channel high gain differential amplifier utilizing enhancement depletion MOS field effect transistors which exhibits high common mode rejection and fast switching characteristics.

Abstract: A process for forming holes with precisely controlled dimension and position in monocrystalline silicon wafers wherein the holes are fabricated with vertical sides. In the preferred process, both sides of the silicon body are masked, opposite registered openings made in the masking layers, an impurity introduced through the openings into the body forming low resistivity regions, the body anodically etched through the openings until a porous silicon region is formed completely through the body, and subsequently removing the resultant porous silicon region with a silicon etchant.

Abstract: A process for forming complete dielectrically isolated monocrystalline silicon regions on a substrate by depositing a first epitaxial silicon layer embodying an N-type impurity on a low resistivity silicon substrate embodying a P-type impurity, forming annular P-type impurity regions in the first epitaxial layer, depositing the second epitaxial layer embodying an N-type impurity on the first epitaxial layer, forming annular P-type impurity regions in the second epitaxial layer in registry with the annular regions in the first epitaxial layer, converting the silicon substrate and the annular P-type regions in the first and second epitaxial layers into porous silicon material by an anodic treatment carried out in an aqueous solution of hydrofluoric acid, and oxidizing the porous silicon material to form silicon oxide.A semiconductor structure having a backing substrate of silicon oxide with monocrystalline silicon islands embedded therein.

Abstract: A field effect transistor with spaced source and drain regions of a first type conductivity in a monocrystalline semiconductor body having a background impurity of a second opposite type conductivity, the improvement being a buried layer of a second type conductivity impurity having an average concentration higher than the impurity concentration of the background impurity that is located just beneath the insulating layer in the field regions of the device and at a greater depth in the gate region, the depth in the gate region being approximately equal to the thickness of the field insulating layer less the thickness of the gate insulating layer.