Patents Assigned to Actel Corporation
  • FIELD PROGRAMMABLE GATE ARRAY INCLUDING A NONVOLATILE USER MEMORY AND METHOD FOR PROGRAMMING
    Publication number: 20090058462
    Abstract: An integrated circuit includes a programmable logic unit and an on-chip non-volatile memory. A JTAG port, TAP controller circuit, and program/erase control circuitry provide user access to the non-volatile memory for storage of user data. The non-volatile memory may also be used to store device data such as a serial number, product identification number, date code, or security data. Portions of the non-volatile memory may be made unavailable to the user once programmed, while other portions of the non-volatile may remain available for user access.
    Type: Application
    Filed: November 5, 2008
    Publication date: March 5, 2009
    Applicant: Actel Corporation
    Inventors: Martin Mason, Theodore Speers
  • REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL
    Publication number: 20090057821
    Abstract: A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer.
    Type: Application
    Filed: October 27, 2008
    Publication date: March 5, 2009
    Applicant: ACTEL CORPORATION
    Inventors: A. Farid Issaq, Frank Hawley, John McCollum
  • Flash/dynamic random access memory field programmable gate array
    Patent number: 7499360
    Abstract: A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: March 3, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Vidya Bellippady, Gregory Bakker
  • Non-volatile look-up table for an FPGA
    Patent number: 7495473
    Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to Vcc through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 24, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Gregory Bakker, Jonathan Greene
  • APPARATUS FOR INTERFACING AND TESTING A PHASE LOCKED LOOP IN A FIELD PROGRAMMABLE GATE ARRAY
    Publication number: 20090045855
    Abstract: An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.
    Type: Application
    Filed: August 26, 2008
    Publication date: February 19, 2009
    Applicant: ACTEL CORPORATION
    Inventors: Wei-Min Kuo, Donald Y. Yu
  • Programmable system on a chip for power-supply voltage and current monitoring and control
    Patent number: 7493506
    Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 17, 2009
    Assignee: Actel Corporation
    Inventors: Rabindranth Balasubramanian, Gregory Bakker
  • Programmable system on a chip for power-supply voltage and current monitoring and control
    Patent number: 7492183
    Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and voltage-measuring and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with voltage-measuring, current-measuring and control circuitry performs voltage measurement and control functions and can be used to control and monitor external power supplies connected to external loads.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 17, 2009
    Assignee: Actel Corporation
    Inventors: Rabindranth Balasubramanian, Gregory Bakker
  • Non-volatile look-up table for an FPGA
    Patent number: 7492182
    Abstract: A non-volatile-memory-transistor based lookup table for an FPGA includes a n:1 multiplexer. A non-volatile memory transistor is coupled to each of the n inputs of the multiplexer. The multiplexer has x address inputs wherein 2x=n as is known in the art. The output of the multiplexer is coupled to VCC through a pullup transistor. The gate of the pullup transistor is coupled to the output of an address transition detector circuit that has inputs coupled to the address inputs of the multiplexer. A sense amplifier is coupled to the output of the multiplexer.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 17, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Gregory Bakker, Jonathan Greene
  • Radiation tolerant SRAM bit
    Patent number: 7486538
    Abstract: In an integrated circuit, a radiation tolerant static random access memory device comprising a first inverter having an input and an output, a second inverter having an input and an output. A first resistor is coupled between the output of the first inverter and the input of the second inverter. A second resistor is coupled between the output of the second inverter and the input of the first inverter. A first write transistor is coupled to the output of the first inverter and has a gate coupled to a source of a first set of write-control signals and a second write transistor is coupled to the output of the second inverter and has a gate coupled to said source of a second set of write-control signals. Finally, a pass transistor has a gate coupled to the output of on of the first and second inverters.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: February 3, 2009
    Assignee: Actel Corporation
    Inventor: John L. McCollum
  • Programmable system on a chip
    Patent number: 7487376
    Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: February 3, 2009
    Assignee: Actel Corporation
    Inventors: Greg Bakker, Khaled El-Ayat, Theodore Speers, Limin Zhu, Brian Schubert, Rabindranath Balasubramanian, Kurt Kolkind, Thomas Barraza, Venkatesh Narayanan, John McCollum, William C. Plants
  • Method and apparatus of memory clearing with monitoring RAM memory cells in a field programmable gated array
    Patent number: 7482835
    Abstract: A field-programmable gate array (FPGA) having an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of the at least one row of RAM memory cells coupled to a row driver line; a row decoder coupled to a first end of the row driver line of each at least one row of RAM memory cells. A monitoring memory cell is coupled to a row driver line. Each monitoring memory cell is also coupled to a memory writing line. An FPGA also has RAM memory cells that act as the programming mechanism. The FPGA further has erase circuitry for clearing the RAM memory cells for reprogramming of the FPGA. The FPGA is erased by providing at least one monitoring memory cell coupled to the erase circuitry. A memory clear phase is initiated on at least one monitoring memory cell. The monitoring memory cell then indicts the cell has been cleared.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: January 27, 2009
    Assignee: Actel Corporation
    Inventors: Chung Sun, Eddy C. Huang
  • Delay locked loop for an FPGA architecture
    Patent number: 7484113
    Abstract: A DLL provides a deskew mode for aligning a reference clock that passes through a clock distribution tree to a feedback by adding additional delay to the feedback clock to align the feedback clock with reference clock at one cycle later. A 0 ns clock-to-out mode is provided by adding additional delay to account for an input buffer into a feedback path. The feedback clock can be doubled by a clock doubler with 50% duty cycle adjustment disposed in the feedback path. Flexible timing is aligning the reference clock to the feedback clock is obtained with additional delay elements disposed in the feedback and reference clock paths.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: January 27, 2009
    Assignee: Actel Corporation
    Inventors: William C. Plants, Nikhil Mazumder, Arunangshu Kundu, James Joseph, Wayne W. Wong
  • Low-capacitance input/output and electrostatic discharge circuit for protecting an integrated circuit from electrostatic discharge
    Patent number: 7482218
    Abstract: A transistor formed on a semiconductor substrate of a first conductivity type in a well formed in the substrate and doped with the first conductivity type to an impurity level higher than that of the substrate. A drain doped to a second conductivity type opposite to said first conductivity type is disposed in the well. A pair of opposed source regions doped to the second conductivity type are disposed in the well and are electrically coupled together. They are separated from opposing outer edges of the drain region by channels. A pair of gates are electrically coupled together and disposed above and insulated from the channels. A region of the well disposed below the drain is doped so as to reduce capacitive coupling between the drain and the well.
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: January 27, 2009
    Assignee: Actel Corporation
    Inventors: John McCollum, Fethi Dhaoui
  • Three input field programmable gate array logic circuit configurable as a three input look up table, a D-latch or a D flip-flop
    Patent number: 7477071
    Abstract: A field programmable gate array logic cell includes a logic circuit having three inputs and at least one output and a plurality of multiplexers having inputs and outputs. The logic circuit also includes a plurality of programmable elements coupled between the three inputs and at least one output of the logic circuit and the inputs and outputs of the plurality of multiplexers such that a plurality of sequential logic units and combinatorial units can be realized by programming selected ones of the programmable elements, the sequential logic units may include a flip-flop.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: January 13, 2009
    Assignee: Actel Corporation
    Inventors: Alan B. Reynolds, Andrew W. Reynolds, Volker Hecht
  • Non-volatile two-transistor programmable logic cell and array layout
    Patent number: 7473960
    Abstract: A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: January 6, 2009
    Assignee: Actel Corporation
    Inventors: Fethi Dhaoui, John McCollum, Vidyadhara Bellippady, William C. Plants, Zhigang Wang
  • CLOCK-GENERATOR ARCHITECTURE FOR A PROGRAMMABLE-LOGIC-BASED SYSTEM ON A CHIP
    Publication number: 20080309393
    Abstract: A programmable system-on-a-chip integrated circuit device comprises at least one of a crystal oscillator circuit, an RC oscillator circuit, and an external oscillator input. A clock conditioning circuit is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A real-time clock is selectively coupleable to one of the programmable logic block, the crystal oscillator circuit, the RC oscillator circuit, and the external oscillator input. A programmable logic block is coupled to the clock conditioning circuit and the real-time clock.
    Type: Application
    Filed: October 31, 2007
    Publication date: December 18, 2008
    Applicant: ACTEL CORPORATION
    Inventors: Shin-Nan Sun, Limin Zhu, Theodore Speers, Gregory Bakker
  • FACE-TO-FACE BONDED I/O CIRCUIT DIE AND FUNCTIONAL LOGIC CIRCUIT DIE SYSTEM
    Publication number: 20080309371
    Abstract: An integrated circuit system includes a first set of integrated circuit dice each member of the set having a different configuration of input/output circuits disposed thereon and a second set of integrated circuit dice each having different logical function circuits disposed thereon. Each member of the first and second sets of integrated circuit dice include an array of face-to-face bonding pads disposed thereon that mate with the array of face-to-face bonding pads of each member of the other set.
    Type: Application
    Filed: August 22, 2008
    Publication date: December 18, 2008
    Applicant: ACTEL CORPORATION
    Inventor: Theodore Speers
  • PROGRAMMABLE SYSTEM ON A CHIP FOR TEMPERATURE MONITORING AND CONTROL
    Publication number: 20080303547
    Abstract: A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.
    Type: Application
    Filed: July 24, 2008
    Publication date: December 11, 2008
    Applicant: Actel Corporation
    Inventors: Rabindranath Balasubramanian, Limin Zhu, Gregory Bakker
  • Apparatus and method for reducing leakage of unused buffers in an integrated circuit
    Patent number: 7463061
    Abstract: A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input node and the input of the buffer, the fixed-state multiplexer input node having a potential of either less than zero volts or more than VCC present on it.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: December 9, 2008
    Assignee: Actel Corporation
    Inventors: Jonathan W. Greene, Vidya Bellippady
  • DEGLITCHING CIRCUITS FOR A RADIATION-HARDENED STATIC RANDOM ACCESS MEMORY BASED PROGRAMMABLE ARCHITECTURE
    Publication number: 20080298116
    Abstract: A method for providing a deglitching circuit for a radiation tolerant static random access memory (SRAM) comprising: providing a configuration memory having a plurality of configuration bits; coupling read and write circuitry to the configuration memory for configuring the plurality of configuration bits; coupling a radiation hard latch to a programmable element, the radiation hard latch controlling the programmable element; and providing an interface that couples at least one of the plurality of configuration bits to the radiation hard latch when the write circuitry writes to the at least one of the plurality of configuration bits.
    Type: Application
    Filed: July 14, 2008
    Publication date: December 4, 2008
    Applicant: ACTEL CORPORATION
    Inventor: William C. Plants