Patents Assigned to Advanced Analogic Technologies, Inc.
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Publication number: 20080252372Abstract: A stereo class-D audio system includes a first die including four monolithically integrated NMOS high-side devices and a second a second die including four monolithically integrated PMOS low-side devices. The audio system also includes a set of electrical contacts for connecting the high and low-side devices to components within the a stereo class-D audio system, the set of electrical contacts including at least one supply contact for connecting the drains of the high-side devices to a supply voltage (Vcc) and at least one ground contact for connecting the drains of the low-side devices to ground, the electrical contacts also including respective contacts for each source of the high and low-side devices allowing the source of each high-side device to be connected to the source of a respective low-side device to form two H-bridge circuits.Type: ApplicationFiled: October 17, 2007Publication date: October 16, 2008Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.Inventor: Richard K. Williams
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Publication number: 20080253152Abstract: A switching regulator that practices the current invention includes a high-side switch M1 connected between an input voltage and a node Lx. A low-side switch is connected between the node Lx and ground. An inductor L is connected between Lx and an output node (VOUT). A filtering capacitor connects VOUT to ground. The switching regulator has two distinct operational phases. During the first operational phase, the high-side switch is OFF and the low-side switch is ON. During the second operational phase, the high-side switch is ON and the low-side switch acts as a current source. During transitions between the second and first operational phases, the low-side switch is controlled to momentarily decrease the regulated drain-to-source current.Type: ApplicationFiled: August 8, 2007Publication date: October 16, 2008Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.Inventors: Kevin D'Angelo, Robert Wrathall
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Patent number: 7432555Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.Type: GrantFiled: May 5, 2005Date of Patent: October 7, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080237656Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. An isolated junction field-effect transistor is formed in the isolated pocket.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237706Abstract: A lateral MOSFET formed in a substrate of a first conductivity type includes a gate formed atop a gate dielectric layer over a surface of the substrate, a drain region of a second conductivity type, a source region of a second conductivity type, and a body region of the first conductivity type which extends under the gate. The body region may have a non-monotonic vertical doping profile with a portion located deeper in the substrate having a higher doping concentration than a portion located shallower in the substrate. The lateral MOSFET may be drain-centric, with the source region and an optional dielectric-filled trench surrounding the drain region.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237704Abstract: An isolation structure for a semiconductor device comprises a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. A MOSFET is formed in the isolated pocket.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237783Abstract: A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080237782Abstract: An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region.Type: ApplicationFiled: December 17, 2007Publication date: October 2, 2008Applicants: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Donald Ray Disney, Wai Tien Chan
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Publication number: 20080230812Abstract: Various integrated circuit devices, in particular a junction field-effect transistor (JFET), are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.Type: ApplicationFiled: February 27, 2008Publication date: September 25, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Donald R. Disney, Richard K. Williams
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Publication number: 20080217729Abstract: An isolated CMOS pair of transistors formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.Type: ApplicationFiled: February 14, 2008Publication date: September 11, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Donald R. Disney, Richard K. Williams
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Publication number: 20080217699Abstract: An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.Type: ApplicationFiled: February 14, 2008Publication date: September 11, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Donald R. Disney, Richard K. Williams
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Patent number: 7422938Abstract: An structure for electrically isolating a semiconductor device is formed by implanting dopant into a semiconductor substrate that does not include an epitaxial layer. Following the implant the structure is exposed to a very limited thermal budget so that dopant does not diffuse significantly. As a result, the dimensions of the isolation structure are limited and defined, thereby allowing a higher packing density than obtainable using conventional processes which include the growth of an epitaxial layer and diffusion of the dopants. In one group of embodiments, the isolation structure includes a deep layer and a sidewall which together form a cup-shaped structure surrounding an enclosed region in which the isolated semiconductor device may be formed. The sidewalls may be formed by a series of pulsed implants at different energies, thereby creating a stack of overlapping implanted regions.Type: GrantFiled: August 14, 2004Date of Patent: September 9, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080213972Abstract: Processes for forming isolation structures for semiconductor devices include forming a submerged floor isolation region and a filed trench which together enclose an isolated pocket of the substrate. One process aligns the trench to the floor isolation region. In another process a second, narrower trench is formed in the isolated pocket and filled with a dielectric material while the dielectric material is deposited so as to line the walls and floor of the first trench. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.Type: ApplicationFiled: February 14, 2008Publication date: September 4, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Donald R. Disney, Richard K. Williams
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Publication number: 20080210980Abstract: Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.Type: ApplicationFiled: February 14, 2008Publication date: September 4, 2008Applicant: Advanced Analogic Technologies, Inc.Inventors: Donald R. Disney, Richard K. Williams
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Patent number: 7419878Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.Type: GrantFiled: September 15, 2005Date of Patent: September 2, 2008Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Publication number: 20080203543Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: ApplicationFiled: April 30, 2008Publication date: August 28, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Publication number: 20080203991Abstract: A DC-DC converter that includes a high frequency power MESFET gate drive circuit is provided. The gate drive circuits are intended to be used in switching regulators where at least one switching device is an N-channel MESFET. For regulators of this type, the gate drive circuits provide gate drive at the correct voltage to ensure that MESFETs are neither under driven (resulting in incorrect circuit operation) nor over driven (resulting in MESFET damage or excess current or power loss).Type: ApplicationFiled: February 18, 2008Publication date: August 28, 2008Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.Inventor: Richard K. Williams
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Publication number: 20080203520Abstract: Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.Type: ApplicationFiled: April 30, 2008Publication date: August 28, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Richard K. Williams
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Publication number: 20080197908Abstract: A cascode power switch for use in a MESFET based switching regulator includes a MOSFET in series with a normally-off MESFET. The cascode power switch is typically connected in between a power source and a node Vx. The node Vx is connected to an output node via an inductor and to ground via a Schottky diode or a second MESFET or both. A control circuit drives the MESFET (and the second MESFET) so that the inductor is alternately connected to the battery and to ground. The MOSFET is switched off during sleep or standby modes to minimize leakage current through the MESFET. The MOSFET is therefore switched at a low frequency compared to the MESFET and does not contribute significantly to switching losses in the converter.Type: ApplicationFiled: February 16, 2008Publication date: August 21, 2008Applicant: ADVANCED ANALOGIC TECHNOLOGIES, INC.Inventor: Richard K. Williams
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Publication number: 20080197827Abstract: A reverse current comparator for use in switching regulators includes a differential stage configured to encode the difference in voltage between an N and a P input. The differential stage feeds one or more gain stages. At least one of the gain stages includes one or more hysteresis devices. When the voltage of the N input exceeds the voltage of the P input by a predetermined margin, the hysteresis device causes the regulator to enter a triggered state in which it outputs a non-zero output voltage. Subsequent changes to the N and P inputs do not change the regulator output until a RESET input is asserted and which point the regulator enters a reset state and is ready to be triggered.Type: ApplicationFiled: February 22, 2008Publication date: August 21, 2008Applicant: Advanced Analogic Technologies, Inc.Inventor: Robert Wrathall
