Patents Assigned to ADVANCED MICRO DEVICES (AMD)
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Patent number: 11658123Abstract: A chip for hybrid bridged fanout chiplet connectivity, the chip comprising: a central chiplet; one or more first chiplets each coupled to the central chiplet using a plurality of fanout traces; and one or more second chiplets each coupled to the central chiplet using one or more interconnect dies (ICDs).Type: GrantFiled: September 25, 2020Date of Patent: May 23, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Rahul Agarwal, Milind S. Bhagavat
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Patent number: 11657014Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.Type: GrantFiled: December 8, 2020Date of Patent: May 23, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Jason R. Talbert
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Patent number: 11658681Abstract: Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.Type: GrantFiled: June 15, 2021Date of Patent: May 23, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Greg Sadowski, John Kalamatianos
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Patent number: 11645073Abstract: Address-based filtering for load/store speculation includes maintaining a filtering table including table entries associated with ranges of addresses; in response to receiving an ordering check triggering transaction, querying the filtering table using a target address of the ordering check triggering transaction to determine if an instruction dependent upon the ordering check triggering transaction has previously been generated a physical address; and in response to determining that the filtering table lacks an indication that the instruction dependent upon the ordering check triggering transaction has previously been generated a physical address, bypassing a lookup operation in an ordering violation memory structure to determine whether the instruction dependent upon the ordering check triggering transaction is currently in-flight.Type: GrantFiled: April 23, 2021Date of Patent: May 9, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: John Kalamatianos, Krishnan V. Ramani, Susumu Mashimo
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Patent number: 11636038Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.Type: GrantFiled: January 13, 2022Date of Patent: April 25, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventor: David A. Roberts
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Patent number: 11631624Abstract: Various semiconductor chip packages are disclosed. In one aspect, a semiconductor chip package is provided that includes a package substrate that has a first edge and a second edge opposite to the first edge. A semiconductor chip is mounted on the package substrate. A thermal interface material is positioned on the semiconductor chip. A lid is positioned over the thermal interface material. A spring biasing mechanism is included that is operable to bias the lid away from the package substrate so that the lid, when subjected to a compressive force, can translate toward the package substrate and impart a compressive force on the thermal interface material.Type: GrantFiled: December 11, 2018Date of Patent: April 18, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Kaushik Mysore Srinivasa Setty, William J. Maxwell
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Patent number: 11630715Abstract: A method and system for recording and logging errors in a computer system includes reading first error handling information with respect to a transaction. The first error handling information is stored in a first component, and based upon a condition of the storage in the first component, an oldest error information is evicted from the first component.Type: GrantFiled: December 22, 2020Date of Patent: April 18, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Philip Ng, Buheng Xu
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Patent number: 11630772Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.Type: GrantFiled: September 29, 2021Date of Patent: April 18, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Paul J. Moyer
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Patent number: 11625249Abstract: Preserving memory ordering between offloaded instructions and non-offloaded instructions is disclosed. An offload instruction for an operation to be offloaded is processed and a lock is placed on a memory address associated with the offload instruction. In response to completing a cache operation targeting the memory address, the lock on the memory address is removed. For multithreaded applications, upon determining that a plurality of processor cores have each begun executing a sequence of offload instructions, the execution of non-offload instructions that are younger than any of the offload instructions is restricted. In response to determining that each processor core has completed executing its sequence of offload instructions, the restriction is removed. The remote device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.Type: GrantFiled: December 29, 2020Date of Patent: April 11, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Jagadish B. Kotra, John Kalamatianos
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Patent number: 11579514Abstract: A system and method for controlling characteristics of collected image data are disclosed. The system and method include performing pre-processing of an image using GPUs, configuring an optic based on the pre-processing, the configuring being designed to account for features of the pre-processed image, acquiring an image using the configured optic, processing the acquired image using GPUs, and determining if the processed acquired image accounts for feature of the pre-processed image, and the determination is affirmative, outputting the image, wherein if the determination is negative repeating the configuring of the optic and re-acquiring the image.Type: GrantFiled: December 23, 2020Date of Patent: February 14, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Allen H. Rush, Hui Zhou
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Patent number: 11573853Abstract: Error checking data used in offloaded operations is disclosed. A remote execution device receives a request from a host to store a data block in a memory region. The data block includes data and host-generated error checking information for the data. The remote execution device updates the data block by overwriting the host-generated error checking information with locally generated error checking information for the data. The data block is then stored in the memory region.Type: GrantFiled: March 31, 2021Date of Patent: February 7, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Vilas Sridharan, Sudhanva Gurumurthi
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Patent number: 11573801Abstract: A processor includes a register file and control logic that detects multiple different sets of sequential zero bits of a register in the register file, wherein each of the multiple different sets has a bit length that corresponds to a partial instruction width and operates at a first partial instruction width or a second partial instruction width with the register file depending on number of sets of zero bits detected in the register. In certain examples, the control logic causes operating at first instruction width that avoids merging of a first bit length of data in the register and operating at the second instruction width that avoids merging of a second bit length of data in the register. In some examples, a register rename map table incudes multiple zero bits that identify the detected multiple different sets of bits of sequential zeros.Type: GrantFiled: September 29, 2021Date of Patent: February 7, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Eric Dixon, Erik Swanson, Theodore Carlson, Ruchir Dalal, Michael Estlick
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Patent number: 11570903Abstract: A process for conformally coating passive surface mount components soldered to a printed circuit substrate of a lidless flip-chip ball grid array package includes affixing a stiffener ring to the substrate before forming a conformal coating on the passive surface mount components. The stiffener ring is affixed to the substrate so that the plurality of passive surface mount components and the integrated circuit die are contained within an opening formed by the stiffener ring. After affixing the stiffener ring to the substrate, the conformal coating is formed on the passive surface mount components. The conformal coating extends over each of the passive surface mount components, around a periphery of each of the passive surface mount components, and under each of the passive surface mount components. A product made according to the process is also disclosed.Type: GrantFiled: December 30, 2019Date of Patent: January 31, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Chiaken Leong, Patrick Kim
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Patent number: 11562459Abstract: A graphics pipeline includes a cache having cache lines that are configured to store data used to process frames in a graphics pipeline. The graphics pipeline is implemented using a processor that processes frames for the graphics pipeline using data stored in the cache. The processor processes a first frame and writes back a dirty cache line from the cache to a memory concurrently with processing of the first frame. The dirty cache line is retained in the cache and marked as clean subsequent to being written back to the memory. In some cases, the processor generates a hint that indicates a priority for writing back the dirty cache line based on a read command occupancy at a system memory controller.Type: GrantFiled: December 21, 2020Date of Patent: January 24, 2023Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Noor Mohammed Saleem Bijapur, Ashish Khandelwal, Laurent Lefebvre, Anirudh R. Acharya
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Patent number: 11551990Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.Type: GrantFiled: August 11, 2017Date of Patent: January 10, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: David A. Roberts, Greg Sadowski, Steven Raasch
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Patent number: 11550722Abstract: Methods, systems, and apparatuses provide support for multiple address spaces in order to facilitate data movement. One system includes a host processor; a memory; a data fabric coupled to the host processor and to the memory; a first input/output memory manage unit (IOMMU) and a second IOMMU, each of the first and second IOMMUs coupled to the data fabric; a first root port and a second root port, each of the first and second root ports coupled to a corresponding IOMMU of the first and second IOMMUs; and a first peripheral component endpoint and a second peripheral component endpoint, each of the first and second peripheral component endpoints coupled to a corresponding root port of the first and second root ports, wherein each of the first and second root ports comprises hardware control logic operative to: synchronize the first and second root ports.Type: GrantFiled: March 2, 2021Date of Patent: January 10, 2023Assignees: ATI TECHNOLOGIES ULC, ADVANCED MICRO DEVICES, INC.Inventors: Philip Ng, Nippon Raval, BuHeng Xu, Rostislav S. Dobrin, Shawn Han
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Publication number: 20220413849Abstract: Providing atomicity for complex operations using near-memory computing is disclosed. In an implementation, a complex atomic operation is decomposed into a set of sequential operations that is stored in a near-memory instruction store. A memory controller receives a request from a host execution engine to issue the complex atomic operation and initiates execution of the stored set of sequential operations on a near-memory compute unit. The complex atomic operation may be a user-defined complex atomic operation.Type: ApplicationFiled: June 28, 2021Publication date: December 29, 2022Applicant: ADVANCED MICRO DEVICES, INC.Inventor: NUWAN JAYASENA
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Patent number: 11537319Abstract: A processing system includes a content addressable memory (CAM) in an input/output path to selectively modify register writes on a per-pipeline basis. The CAM compares an address of a register write to an address field of each entry of the CAM. If a match is found, the CAM modifies the register write data as defined by a function for the matching entry of the CAM. In some embodiments, each entry of the CAM includes a data mask defining subfields of the register write data, wherein each subfield includes subfield data including one or more bits.Type: GrantFiled: December 11, 2019Date of Patent: December 27, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Alexander Fuad Ashkar, James R. Klobcar, Harry J. Wise
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Patent number: 11527033Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.Type: GrantFiled: March 20, 2020Date of Patent: December 13, 2022Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Saad Arrabi, Vishrut Vaibhav, Mangesh P. Nijasure, Todd Martin
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Patent number: 11507158Abstract: Electrical design current throttling, including: applying an electrical design current (EDC) threshold for each control processing unit component of a plurality of the central processing unit components responsive to the corresponding priority of each central processing unit component, the priority of a central processing unit component responsive to a central processing unit component's current usage data.Type: GrantFiled: May 12, 2020Date of Patent: November 22, 2022Assignees: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULCInventors: Xiuting Kaleen Cheng Man, Erik Swanson, Larry D. Hewitt, Adam N. C. Clark
